Single Cycle Processor

Welcome! thanks for visiting

Description

This is a simple implementation of a single cycle processor. specifications:

see wiki for more detailes.

add all .v files to a new project in modelsim and simulate it. You can add your commands in instructions.txt and your datas in datas.txt

This project is done by Zahra Mousavi and Ghazal Minaei.

Thanks for reading this!

Name		Name	Last commit message	Last commit date
Latest commit History 53 Commits
images		images
.gitignore		.gitignore
ALU.v		ALU.v
CA#02.pdf		CA#02.pdf
CU.v		CU.v
Concatenator.v		Concatenator.v
DP.v		DP.v
README.md		README.md
adder.v		adder.v
aluCU.v		aluCU.v
dataMemory.v		dataMemory.v
datas.txt		datas.txt
instAsm.s		instAsm.s
instructionMemory.v		instructionMemory.v
instructions.txt		instructions.txt
mips.v		mips.v
mux2.v		mux2.v
mux3.v		mux3.v
new		new
regFile.v		regFile.v
register.v		register.v
test.v		test.v
testBench.v		testBench.v