- 👋 Hi, I’m @habibhossam
- 👀 I’m interested in IC design
- 🌱 I’m currently learning Verilog, VLSI,
- 💞️ I’m looking to collaborate on new design projects and implementations on FPGA
- 📫 How to reach me habibhossam123@gmail.com
Popular repositories Loading
-
Complete-ASIC-Flow-of-I2C-communication-protocol
Complete-ASIC-Flow-of-I2C-communication-protocol PublicVerilog 1
-
-
Full-Custom_SDES
Full-Custom_SDES PublicThe primary objective of this project is to design and implement a Simplified Data Encryption Standard (S-DES) algorithm, which retains the essential features of the DES algorithm but with much sma…
SourcePawn
-
Verification-of-SPI-slave-IP-with-SystemVerilog
Verification-of-SPI-slave-IP-with-SystemVerilog PublicHTML
-
Design-and-optimization-of-fully-differential-discrete-time-2nd-order-sigma-delta-ADC
Design-and-optimization-of-fully-differential-discrete-time-2nd-order-sigma-delta-ADC PublicIn this project, we aim to design and optimize a fully differential sigma-delta ADC that achieves exceptional performance in terms of noise shaping, signal-to-noise ratio (SNR), and bandwidth.
-
Design-of-an-RF-Front-End-of-a-Receiver-Chain
Design-of-an-RF-Front-End-of-a-Receiver-Chain Publicdesign and simulate the LNA and Mixer blocks independently to ensure their individual functionality. Subsequently, the two blocks are integrated and simulated together to validate their combined fu…
If the problem persists, check the GitHub status page or contact support.