Add Intel APX and AVX10 target flags and LLVM attribute setting.

python_bindings/src/halide/halide_/PyEnums.cpp

@@ -194,6 +194,8 @@ void define_enums(py::module &m) {
         .value("VulkanV12", Target::VulkanV12)
         .value("VulkanV13", Target::VulkanV13)
         .value("Semihosting", Target::Feature::Semihosting)
+        .value("AVX10_1", Target::Feature::AVX10_1)
+        .value("X86APX", Target::Feature::X86APX)
         .value("FeatureEnd", Target::Feature::FeatureEnd);
 
     py::enum_<halide_type_code_t>(m, "TypeCode")

src/CodeGen_X86.cpp

@@ -54,6 +54,10 @@ Target complete_x86_target(Target t) {
     if (t.has_feature(Target::AVX)) {
         t.set_feature(Target::SSE41);
     }
+
+    // TODO(resolve before landing): Fill in for AVX10_1.
+    // TODO(resolve before landing): Is there anything to do here for X86APX?
+
     return t;
 }
 
@@ -1034,6 +1038,28 @@ string CodeGen_X86::mattrs() const {
         attrs.push_back("+prefer-no-gather");
     }
 #endif
+
+    if (target.has_feature(Target::AVX10_1)) {
+      switch (target.vector_bits) {
+        case 256:
+          attrs.push_back("+avx10.1-256");
+          break;
+        case 512:
+          attrs.push_back("+avx10.1-512");
+          break;
+        default:
+          user_error << "AVX10 only supports 256 or 512 bit variants at present.\n";
+          break;
+      }
+    }
+
+    if (target.has_feature(Target::X86APX)) {
+        attrs.push_back("egpr");
+        attrs.push_back("push2pop2");
+        attrs.push_back("ppx");
+        attrs.push_back("ndd");
+    }
+
     return join_strings(attrs, ",");
 }
 
@@ -1042,7 +1068,9 @@ bool CodeGen_X86::use_soft_float_abi() const {
 }
 
 int CodeGen_X86::native_vector_bits() const {
-    if (target.has_feature(Target::AVX512) ||
+    if (target.has_feature(Target::AVX10_1)) {
+        return target.vector_bits;
+    } else if (target.has_feature(Target::AVX512) ||
         target.has_feature(Target::AVX512_Skylake) ||
         target.has_feature(Target::AVX512_KNL) ||
         target.has_feature(Target::AVX512_Cannonlake)) {

src/Target.cpp

@@ -293,6 +293,9 @@ Target calculate_host_target() {
             }
         }
     }
+
+    // TODO(resolve before landing): Fill in for AVX10_1.
+    // TODO(resolve before landing): Fill in for X86APX.
 #endif
 #endif
 #endif
@@ -557,6 +560,8 @@ const std::map<std::string, Target::Feature> feature_name_map = {
     {"vk_v12", Target::VulkanV12},
     {"vk_v13", Target::VulkanV13},
     {"semihosting", Target::Semihosting},
+    {"avx10_1", Target::AVX10_1},
+    {"x86apx", Target::X86APX},
     // NOTE: When adding features to this map, be sure to update PyEnums.cpp as well.
 };
 

src/Target.h

@@ -168,6 +168,8 @@ struct Target {
         VulkanV12 = halide_target_feature_vulkan_version12,
         VulkanV13 = halide_target_feature_vulkan_version13,
         Semihosting = halide_target_feature_semihosting,
+        AVX10_1 = halide_target_feature_avx10_1,
+        X86APX = halide_target_feature_x86_apx,
         FeatureEnd = halide_target_feature_end
     };
     Target() = default;

src/runtime/HalideRuntime.h

@@ -1421,6 +1421,8 @@ typedef enum halide_target_feature_t {
     halide_target_feature_vulkan_version12,       ///< Enable Vulkan v1.2 runtime target support.
     halide_target_feature_vulkan_version13,       ///< Enable Vulkan v1.3 runtime target support.
     halide_target_feature_semihosting,            ///< Used together with Target::NoOS for the baremetal target built with semihosting library and run with semihosting mode where minimum I/O communication with a host PC is available.
+    halide_target_feature_avx10_1,                ///< Intel AVX10 version 1 support. vector_bits is used to indicate width.
+    halide_target_feature_x86_apx,                ///< Intel x86 APX support. Covers initial set of features released as APX: egpr,push2pop2,ppx,ndd .
     halide_target_feature_end                     ///< A sentinel. Every target is considered to have this feature, and setting this feature does nothing.
 } halide_target_feature_t;
 

test/correctness/simd_op_check_x86.cpp

@@ -658,6 +658,7 @@ int main(int argc, char **argv) {
     return SimdOpCheckTest::main<SimdOpCheckX86>(
         argc, argv,
         {
+#if 0
             Target("x86-32-linux"),
             Target("x86-32-linux-sse41"),
             // Always turn on f16c when using avx. Sandy Bridge had avx without
@@ -673,5 +674,8 @@ int main(int argc, char **argv) {
             Target("x86-64-linux-sse41-avx-f16c-avx2-avx512-avx512_skylake-avx512_cannonlake"),
             Target("x86-64-linux-sse41-avx-f16c-avx2-avx512-avx512_skylake-avx512_cannonlake-avx512_zen4"),
             Target("x86-64-linux-sse41-avx-f16c-avx2-avx512-avx512_skylake-avx512_cannonlake-avx512_zen4-avx512_sapphirerapids"),
+#else
+            Target("x86-64-linux-avx10_1-vector_bits_256-x86apx"),
+#endif
         });
 }