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I need a latch (whose output Q is initially 0) that has a three-state input D and if that is at a high impedance, then the output is unchanged. For example, if the input D goes 0, Z, 1, Z, 0, 1, Z, 1, 0, Z, then the output should go 0, 0, 1, 1, 0, 1, 1, 1, 0, 0. My attempt is shown below. But this doesn't work as I want it. What happens is if the input is Z, then the output is unpredictable. I tried using the built-in RS latch (see below) but it also doesn't work as I want it. (A high-impedance input causes an unpredictable output.) Is there a way to create the component that I want using the Digital software? |
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Replies: 3 comments 12 replies
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I think this contraption does what you want... maybe.... ;-) |
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When a real circuit is built in CMOS technology, an open input is unpredictable and can damage the circuit. And also in TTL an open input is not advisable, although it is recognized as high. The simulator simulates this "unpredictability" by generating random values. |
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When a real circuit is built in CMOS technology, an open input is unpredictable and can damage the circuit. And also in TTL an open input is not advisable, although it is recognized as high. The simulator simulates this "unpredictability" by generating random values.
But you can detect high-z in the simulator with a special circuit, and build an according logic.