Gate Delays

[SohamTilekar]

How Can I have a Gate Delay in the Digital for the Simulation like the Logisim?

[hneemann]

In Digital each gate has the same propagation time. This cannot be changed.
However, an additional delay component can be inserted in which the propagation time can be set.

[SohamTilekar]

What is the propagation time.

[hneemann]

The propagation time or propagation delay is the time it takes for the change at one of the inputs to have an effect on the corresponding output. This is essentially determined by how quickly the transistors that make up the gate can switch between "conducting" and "non-conducting" and vice versa.

[SohamTilekar]

No No, I was Asking what is the Propagation time simulated in the Digital.

[hneemann]

There is no defined value for the propagation delay. However, the simulation algorithm ensures that all gates have the same propagation delay, and its value depends on how fast the processor running the simulation is and on the number of gates. If the number of gates doubles, the calculation of all state changes takes twice as long and the propagation delay appears to double as well.

[mengstr]

With the domain knowledge you have acquired over the years while developing Digital, if you now were to rewrite Digital from scratch (I.E Digital 2.0) would you add settable gate delays as well as the possibility to simulate the timings taken from data sheets for entire 40xx and 74-xx logic families?

[hneemann]

No, I wouldn't. And that's because my goals haven't changed. Although I use the simulator to demonstrate the oscillation of an RS-FF, it is still mostly used by me to teach the function and programming of processors. And to do that, performance is important: the simulated processor should run fast enough to be able to execute more complex programs quickly.

If all gates have the same propagation time, this is enough to show the oscillation of an RS-FF. Without this, no meaningful simulation would be possible. If different propagation times were allowed, the reactions of the gates would have to be sorted in time: Which happens first, which happens after. In addition, a whole series of special cases would arise that would have to be dealt with: For example, what should happen if an input changes several times during the propagation delay of the gate? All this would cost performance without bringing much benefit in my eyes.

Simulating propagation times makes little sense - at least at the level of this simulator. Even when developing circuits for an FPGA, the propagation times are more or less random. It depends on how many and which cells are used for routing and placement. Therefore, after synthesis, routing and placement, a separate simulation of the propagation times is also required: only after routing and placement you can calculate which propagation times have resulted and whether it will work. And even then, this is often only used to check whether the circuit reaches the desired clock frequency. But I am not an expert in FPGA design, maybe someone knows better.

That's why I think micromanaging propagation delays is superfluous. And worse, if fine tuning of propagation delays is required to make a circuit work, that's probably the worst thing you can do. At least in the general case, there may be special cases where this is quite interesting. An edge-controlled D-FF, for example, is such a special case.