cpu/atmega_common: checking features instead of CPU RIOT-OS#2

hugueslarrive · Jun 20, 2023 · 6d39173 · 6d39173
1 parent 4529455
commit 6d39173
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Showing 9 changed files with 98 additions and 78 deletions.
diff --git a/cpu/atmega_common/atmega_cpu.c b/cpu/atmega_common/atmega_cpu.c
@@ -60,7 +60,7 @@ void avr8_reset_cause(void)
             DEBUG("Watchdog reset!\n");
         }
     }
-#if !defined (CPU_ATMEGA328P) && !defined (CPU_ATMEGA8)
+#if defined(JTRF)
     if (mcusr_mirror & (1 << JTRF)) {
         DEBUG("JTAG reset!\n");
     }
@@ -89,7 +89,7 @@ ISR(BADISR_vect)
 {
     avr8_reset_cause();
 
-#if defined (CPU_ATMEGA256RFR2)
+#if defined(CPU_ATMEGA256RFR2)
     printf("IRQ_STATUS %#02x\nIRQ_STATUS1 %#02x\n",
             (unsigned int)IRQ_STATUS, (unsigned int)IRQ_STATUS1);
 
@@ -105,7 +105,7 @@ ISR(BADISR_vect)
     core_panic(PANIC_GENERAL_ERROR, "BADISR");
 }
 
-#if defined(CPU_ATMEGA128RFA1) || defined (CPU_ATMEGA256RFR2)
+#if defined(BAT_LOW_vect)
 ISR(BAT_LOW_vect, ISR_BLOCK)
 {
     avr8_enter_isr();

diff --git a/cpu/atmega_common/include/atmega_regs_common.h b/cpu/atmega_common/include/atmega_regs_common.h
@@ -84,18 +84,18 @@ typedef struct {
  * @brief   UART register map
  */
 typedef struct {
-#ifndef CPU_ATMEGA8
+#if defined(UCSR0A) || defined(UCSR1A)
     REG8    CSRA;               /**< control and status register A */
     REG8    CSRB;               /**< control and status register B */
     REG8    CSRC;               /**< control and status register C */
-#ifdef CPU_ATMEGA32U4
+#ifdef UCSR1D /* 32u4 */
     REG8    CSRD;               /**< control and status register D */
 #else
     REG8    reserved;           /**< reserved */
 #endif
     REG16   BRR;                /**< baud rate register */
     REG8    DR;                 /**< data register */
-#else /* atmega8 */
+#elif defined(UCSRA) /* atmega8 */
     REG8    BRRL;               /**< baud rate register low byte */
     REG8    CSRB;               /**< control and status register B */
     REG8    CSRA;               /**< control and status register A */

diff --git a/cpu/atmega_common/include/periph_cpu_common.h b/cpu/atmega_common/include/periph_cpu_common.h
@@ -63,15 +63,27 @@ typedef uint8_t gpio_t;
  *
  * Must be identical to the address of `PINA` provided by avr/io.h
  */
-#ifdef CPU_ATMEGA8
+#if (defined(OCF1A) && defined(OCF1B) && (OCF1A > OCF1B)) \
+    || (defined(PUD) && (PUD != 4)) || (defined(INT0) && (INT0 == 6))
+    /* match with 65 devices against 61 for (PORTB == _SFR_IO8(0x18)) which
+     * did not work here anyway */
 #define GPIO_PORT_DESCENDENT
 #endif
 
 #ifdef GPIO_PORT_DESCENDENT
-#define ATMEGA_GPIO_BASE_A     (0x39)
+#ifdef      _AVR_ATTINY1634_H_INCLUDED
+/*          the only one that requires particular treatment! */
+#define     ATMEGA_GPIO_BASE_A  (0x2F)
 #else
-#define ATMEGA_GPIO_BASE_A      (0x20)
-#endif
+/*          oll other port descendent, including :
+             - _AVR_IO8534_ (only have port A but with 0x18 address) ;
+             - _AVR_IOAT94K_H_ (only have ports D and E) ;
+             - _AVR_IOTN28_H_ (only have ports A and D). */
+#define     ATMEGA_GPIO_BASE_A  (0x39)
+#endif /*   _AVR_ATTINY1634_H_INCLUDED */
+#else /* !GPIO_PORT_DESCENDENT */
+#define     ATMEGA_GPIO_BASE_A  (0x20)
+#endif /* GPIO_PORT_DESCENDENT */
 /**
  * @brief   Base of the GPIO port G register as memory address
  *

diff --git a/cpu/atmega_common/periph/adc.c b/cpu/atmega_common/periph/adc.c
@@ -67,24 +67,39 @@ int adc_init(adc_t line)
 #endif
 
     /* Set ADC-pin as input */
-#if defined(CPU_ATMEGA328P) || defined(CPU_ATMEGA8)
+#if !defined(PORTA) && defined(PC0)
+    /* 328p and 8 do not have PORTA, on 32u4 pins are named differently
+     * and it only have PORTC6 and PORTC7 */
     DDRC &= ~(1 << line);
     PORTC &= ~(1 << line);
-#elif defined(CPU_ATMEGA1284P)
+#elif defined(PORTA) && !defined(DIDR2)
+    /* 1284p do not have DIDR2 */
     DDRA &= ~(1 << line);
     PORTA &= ~(1 << line);
-#elif defined(CPU_ATMEGA2560) || defined(CPU_ATMEGA1281)
+#elif defined(PORTF)
     if (line < 8) {
         DDRF  &= ~(1 << line);
         PORTF &= ~(1 << line);
     }
-#if defined(CPU_ATMEGA2560)
+#if defined(PORTK)
     else {
-        DDRK  &= ~(1 << (line-8));
-        PORTK &= ~(1 << (line-8));
+        DDRK  &= ~(1 << (line - 8));
+        PORTK &= ~(1 << (line - 8));
     }
-#endif /* CPU_ATMEGA2560 */
-#endif /* CPU_ATMEGA328P */
+#elif defined(PORTF0) && !defined(PORTF2) && !defined(PORTF3)
+    /* 32u4 do not have PORTF2 and PORTF3 */
+    else if (line == 8) {
+        DDRD  &= ~(1 << PORTD4);
+        PORTD &= ~(1 << PORTD4);
+    else if (line < 11) {
+        DDRD  &= ~(1 << (line - 3));
+        PORTD &= ~(1 << (line - 3));
+    else {
+        DDRB  &= ~(1 << (line - 7));
+        PORTB &= ~(1 << (line - 7));
+    }
+#endif /* PORTK */
+#endif /* PORTF */
 
     /* set clock prescaler to get the maximal possible ADC clock value */
     for (uint32_t clk_div = 1; clk_div < 8; ++clk_div) {

diff --git a/cpu/atmega_common/periph/i2c.c b/cpu/atmega_common/periph/i2c.c
@@ -49,9 +49,7 @@
 static int _start(uint8_t address, uint8_t rw_flag);
 static int _write(const uint8_t *data, int length);
 static void _stop(void);
-#ifdef PRR
 static void i2c_poweron(i2c_t dev);
-#endif
 
 static mutex_t locks[I2C_NUMOF];
 
@@ -123,10 +121,8 @@ void i2c_init(i2c_t dev)
     /* set pull-up on SCL and SDA */
     I2C_PORT_REG |= (I2C_PIN_MASK);
 
-#ifdef PRR
     /* enable I2C clock */
     i2c_poweron(dev);
-#endif
 
     /* disable device */
     TWCR &= ~(1 << TWEN);
@@ -240,14 +236,14 @@ void i2c_release(i2c_t dev)
     mutex_unlock(&locks[dev]);
 }
 
-#ifdef PRR
 static void i2c_poweron(i2c_t dev)
 {
     assert(dev < I2C_NUMOF);
     (void) dev;
+#ifdef PRTWI
     power_twi_enable();
-}
 #endif
+}
 
 static int _start(uint8_t address, uint8_t rw_flag)
 {

diff --git a/cpu/atmega_common/periph/pwm.c b/cpu/atmega_common/periph/pwm.c
@@ -127,7 +127,7 @@ uint32_t pwm_init(pwm_t dev, pwm_mode_t mode, uint32_t freq, uint16_t res)
     pwm_conf[dev].dev->OCR = 0;
 #endif
 
-#ifdef PRR
+#if defined(PRT2) || defined(PRTIM2) || defined(PRT0) || defined(PRTIM0)
     /* disable power reduction */
     if (dev) {
         power_timer2_enable();
@@ -206,7 +206,7 @@ void pwm_set(pwm_t dev, uint8_t ch, uint16_t value)
 void pwm_poweron(pwm_t dev)
 {
     assert(dev < PWM_NUMOF);
-#ifdef PRR
+#if defined(PRT2) || defined(PRTIM2) || defined(PRT0) || defined(PRTIM0)
     /* disable power reduction */
     if (dev) {
         power_timer2_enable();

diff --git a/cpu/atmega_common/periph/spi.c b/cpu/atmega_common/periph/spi.c
@@ -45,7 +45,7 @@ static mutex_t lock = MUTEX_INIT;
 void spi_init(spi_t bus)
 {
     assert(bus == 0);
-#ifndef CPU_ATMEGA8
+#ifdef PRSPI
     /* power off the SPI peripheral */
     power_spi_disable();
 #endif
@@ -57,13 +57,13 @@ void spi_init_pins(spi_t bus)
 {
     (void)bus;
     /* set SPI pins as output */
-#if defined (CPU_ATMEGA2560) || defined (CPU_ATMEGA1281)
+#if defined(CPU_ATMEGA2560) || defined(CPU_ATMEGA1281)
     DDRB |= ((1 << DDB2) | (1 << DDB1) | (1 << DDB0));
 #endif
-#if defined (CPU_ATMEGA328P) || defined (CPU_ATMEGA8)
+#if defined(CPU_ATMEGA328P) || defined(CPU_ATMEGA8)
     DDRB |= ((1 << DDB2) | (1 << DDB3) | (1 << DDB5));
 #endif
-#if defined (CPU_ATMEGA1284P)
+#if defined(CPU_ATMEGA1284P)
     DDRB |= ((1 << DDB4) | (1 << DDB5) | (1 << DDB7));
 #endif
 #if defined(CPU_ATMEGA128RFA1) || defined(CPU_ATMEGA256RFR2)
@@ -90,7 +90,7 @@ void spi_acquire(spi_t bus, spi_cs_t cs, spi_mode_t mode, spi_clk_t clk)
 
     /* lock the bus and power on the SPI peripheral */
     mutex_lock(&lock);
-#ifndef CPU_ATMEGA8
+#ifdef PRSPI
     power_spi_enable();
 #endif
 
@@ -108,7 +108,7 @@ void spi_release(spi_t bus)
     (void)bus;
     /* power off and release the bus */
     SPCR &= ~(1 << SPE);
-#ifndef CPU_ATMEGA8
+#ifdef PRSPI
     power_spi_disable();
 #endif
     mutex_unlock(&lock);

diff --git a/cpu/atmega_common/periph/timer.c b/cpu/atmega_common/periph/timer.c
@@ -136,7 +136,7 @@ int timer_init(tim_t tim, uint32_t freq, timer_cb_t cb, void *arg)
     /* stop and reset timer */
     ctx[tim].dev->CRA = 0;
     ctx[tim].dev->CRB = 0;
-#ifndef CPU_ATMEGA8
+#ifdef TCCR1C
     ctx[tim].dev->CRC = 0;
 #endif
     ctx[tim].dev->CNT = 0;
@@ -162,12 +162,12 @@ int timer_set_absolute(tim_t tim, int channel, unsigned int value)
     unsigned state = irq_disable();
 
     ctx[tim].dev->OCR[channel] = (uint16_t)value;
-#ifndef CPU_ATMEGA8
+#if defined(OCF1A) && defined(OCF1B) && (OCF1A < OCF1B)
     /* clear spurious IRQs, if any */
-    *ctx[tim].flag = (1 << (channel + OCF1A));
+    *ctx[tim].flag = (1 << (OCF1A + channel));
     /* unmask IRQ */
-    *ctx[tim].mask |= (1 << (channel + OCIE1A));
-#else /* atmega8 */
+    *ctx[tim].mask |= (1 << (OCIE1A + channel));
+#elif defined(OCF1A) && defined(OCF1B) && (OCF1A > OCF1B)
     /* clear spurious IRQs, if any */
     *ctx[tim].flag = (1 << (OCF1A - channel));
     /* unmask IRQ */
@@ -190,12 +190,12 @@ int timer_set(tim_t tim, int channel, unsigned int timeout)
     unsigned absolute = ctx[tim].dev->CNT + timeout;
 
     ctx[tim].dev->OCR[channel] = absolute;
-#ifndef CPU_ATMEGA8
+#if defined(OCF1A) && defined(OCF1B) && (OCF1A < OCF1B)
     /* clear spurious IRQs, if any */
-    *ctx[tim].flag = (1 << (channel + OCF1A));
+    *ctx[tim].flag = (1 << (OCF1A + channel));
     /* unmask IRQ */
-    *ctx[tim].mask |= (1 << (channel + OCIE1A));
-#else /* atmega8 */
+    *ctx[tim].mask |= (1 << (OCIE1A + channel));
+#elif defined(OCF1A) && defined(OCF1B) && (OCF1A > OCF1B)
     /* clear spurious IRQs, if any */
     *ctx[tim].flag = (1 << (OCF1A - channel));
     /* unmask IRQ */
@@ -207,9 +207,9 @@ int timer_set(tim_t tim, int channel, unsigned int timeout)
         /* Timer already expired. Trigger the interrupt now and loop until it
          * is triggered.
          */
-#ifndef CPU_ATMEGA8
+#if defined(OCF1A) && defined(OCF1B) && (OCF1A < OCF1B)
         while (!(*ctx[tim].flag & (1 << (OCF1A + channel)))) {
-#else
+#elif defined(OCF1A) && defined(OCF1B) && (OCF1A > OCF1B)
         while (!(*ctx[tim].flag & (1 << (OCF1A - channel)))) {
 #endif
             ctx[tim].dev->OCR[channel] = ctx[tim].dev->CNT;
@@ -237,12 +237,12 @@ int timer_set_periodic(tim_t tim, int channel, unsigned int value, uint8_t flags
 
     ctx[tim].dev->OCR[channel] = (uint16_t)value;
 
-#ifndef CPU_ATMEGA8
+#if defined(OCF1A) && defined(OCF1B) && (OCF1A < OCF1B)
     /* clear spurious IRQs, if any */
-    *ctx[tim].flag = (1 << (channel + OCF1A));
+    *ctx[tim].flag = (1 << (OCF1A + channel));
     /* unmask IRQ */
-    *ctx[tim].mask |= (1 << (channel + OCIE1A));
-#else /* atmega8 */
+    *ctx[tim].mask |= (1 << (OCIE1A + channel));
+#elif defined(OCF1A) && defined(OCF1B) && (OCF1A > OCF1B)
     /* clear spurious IRQs, if any */
     *ctx[tim].flag = (1 << (OCF1A - channel));
     /* unmask IRQ */
@@ -282,9 +282,9 @@ int timer_clear(tim_t tim, int channel)
         return -1;
     }
 
-#ifndef CPU_ATMEGA8
-    *ctx[tim].mask &= ~(1 << (channel + OCIE1A));
-#else
+#if defined(OCIE1A) && defined(OCIE1B) && (OCIE1A < OCIE1B)
+    *ctx[tim].mask &= ~(1 << (OCIE1A + channel));
+#elif defined(OCIE1A) && defined(OCIE1B) && (OCIE1A > OCIE1B)
     *ctx[tim].mask &= ~(1 << (OCIE1A - channel));
 #endif
 
@@ -326,11 +326,7 @@ static inline void _isr(tim_t tim, int chan)
     avr8_enter_isr();
 
     if (is_oneshot(tim, chan)) {
-#ifndef CPU_ATMEGA8
-        *ctx[tim].mask &= ~(1 << (chan + OCIE1A));
-#else
-        *ctx[tim].mask &= ~(1 << (OCIE1A - chan));
-#endif
+        timer_clear(tim, chan);
     }
     ctx[tim].cb(ctx[tim].arg, chan);