-
Notifications
You must be signed in to change notification settings - Fork 110
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Glayout LLM + Docs + Notebooks #306
Conversation
test cases
added parameters/fixed routes
@@ -0,0 +1,4 @@ | |||
# Common Drain Amplifier | |||
The purpose of a common drain amplifier, aka a source follower, is to provide buffering. It has high input impedance, low output impedance, and a voltage gain close to unity. |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
maybe provide a separate example of a source follower being used in buffering. The LLM might place just a common drain stage as a buffer, which isn't the most ideal
@@ -0,0 +1,12 @@ | |||
# Current Mirror | |||
A current mirror is a circuit designed to copy a current |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
designed to copy a current
copy or boost a current
@@ -0,0 +1,3 @@ | |||
# Strong Arm Latch | |||
A strong arm latch is a comparator (which means it compares two input voltages). If one voltage is higher it outputs a high voltage and if one of them is lower then it output a low voltage. |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
this doesn't really make sense, might cause training problems
The pmos is above the nmos and it's source is tied to vdd. The nmos source is tied to ground. The nmos drain and pmos drain are routed together. The node connecting the nmos and pmos drain is the output node. Additonally, the nmos gate and pmos gate are connected. The node connecting the nmos and pmos gate is the input node. |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
can merge these two lines
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
@alibillalhammoud @chetanyagoyal We want these convos to be in the llm folder?
@@ -3,7 +3,7 @@ | |||
# Apache License |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
Should we have a header with a little more details?
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
and comments..
Please add my comments as issues to fix later. |
Glayout LLM v1
We are getting decent results with the 7b model. It is highly versatile on 2-4 transistor circuits. Current model config: