Remove LPSPI chip select type state, and other refactors

.github/workflows/rust.yml

@@ -138,6 +138,24 @@ jobs:
     - name: Run unit, integration tests
       run: cargo test --features=${{ matrix.chips }} --tests --package=imxrt-hal --package=imxrt-log
 
+  # Make sure our unit tests can pass (some recent version of) miri.
+  miri:
+    needs: tests
+    strategy:
+      matrix:
+        chips:
+        - imxrt-ral/imxrt1011,imxrt1010
+        - imxrt-ral/imxrt1021,imxrt1020
+        - imxrt-ral/imxrt1062,imxrt1060
+        - imxrt-ral/imxrt1176_cm7,imxrt1170
+    runs-on: ubuntu-latest
+    steps:
+    - uses: actions/checkout@v4
+    - name: Install a nightly toolchain with miri
+      run: rustup toolchain install nightly --no-self-update --profile minimal --component miri
+    - name: Run unit, integration tests with miri
+      run: cargo +nightly miri test --features=${{ matrix.chips }} --tests --package=imxrt-hal --package=imxrt-log --config "profile.dev.opt-level = 0"
+
   # Ensures that documentation builds, and that links are valid
   docs:
     needs: format

CHANGELOG.md

@@ -16,7 +16,13 @@
 - `timer::*PitChan`
 - `lpspi::Disabled::{set_mode, set_watermark}`
 
-**BREAKING** `LpspiError::{Busy, NoData}` are removed as possible LPSPI errors.
+**BREAKING** Change the LPSPI driver:
+
+- `LpspiError::{Busy, NoData}` are removed as possible LPSPI errors.
+- There is no more `PCS0` type state associated with the LPSPI bus.
+
+Introduce a hardware chip select and SPI mode into each LPSPI transaction.
+Add an LPSPI configuration for hardware chip selects.
 
 **BREAKING** The following peripherals are not available on the 1180. Therefore,
 they are no longer considered common. However, their APIs are unchanged, and they

board/src/imxrt1010evk.rs

@@ -64,9 +64,11 @@ pub type SpiPins = hal::lpspi::Pins<
     iomuxc::gpio_ad::GPIO_AD_04, // SDO, J57_8
     iomuxc::gpio_ad::GPIO_AD_03, // SDI, J57_10
     iomuxc::gpio_ad::GPIO_AD_06, // SCK, J57_12
-    iomuxc::gpio_ad::GPIO_AD_05, // PCS0, J57_6
 >;
 
+/// SPI PCS0 (J57_6).
+pub type SpiPcs0 = iomuxc::gpio_ad::GPIO_AD_05;
+
 #[cfg(feature = "spi")]
 pub type Spi = hal::lpspi::Lpspi<SpiPins, 1>;
 
@@ -192,8 +194,11 @@ impl Specifics {
                 sdo: iomuxc.gpio_ad.p04,
                 sdi: iomuxc.gpio_ad.p03,
                 sck: iomuxc.gpio_ad.p06,
-                pcs0: iomuxc.gpio_ad.p05,
             };
+            crate::iomuxc::lpspi::prepare({
+                let pcs0: &mut SpiPcs0 = &mut iomuxc.gpio_ad.p05;
+                pcs0
+            });
             let mut spi = Spi::new(lpspi1, pins);
             spi.disabled(|spi| {
                 spi.set_clock_hz(super::LPSPI_CLK_FREQUENCY, super::SPI_BAUD_RATE_FREQUENCY);

board/src/imxrt1060evk.rs

@@ -62,8 +62,9 @@ pub type SpiPins = hal::lpspi::Pins<
     iomuxc::gpio_sd_b0::GPIO_SD_B0_02, // SDO, J24_4
     iomuxc::gpio_sd_b0::GPIO_SD_B0_03, // SDI, J24_5
     iomuxc::gpio_sd_b0::GPIO_SD_B0_00, // SCK, J24_6
-    iomuxc::gpio_sd_b0::GPIO_SD_B0_01, // PCS0, J24_3
 >;
+/// SPI PCS0 (J24_3).
+pub type SpiPcs0 = iomuxc::gpio_sd_b0::GPIO_SD_B0_01;
 
 #[cfg(not(feature = "spi"))]
 /// Activate the `"spi"` feature to configure the SPI peripheral.
@@ -180,8 +181,11 @@ impl Specifics {
                 sdo: iomuxc.gpio_sd_b0.p02,
                 sdi: iomuxc.gpio_sd_b0.p03,
                 sck: iomuxc.gpio_sd_b0.p00,
-                pcs0: iomuxc.gpio_sd_b0.p01,
             };
+            crate::iomuxc::lpspi::prepare({
+                let pcs0: &mut SpiPcs0 = &mut iomuxc.gpio_sd_b0.p01;
+                pcs0
+            });
             let mut spi = Spi::new(lpspi1, pins);
             spi.disabled(|spi| {
                 spi.set_clock_hz(super::LPSPI_CLK_FREQUENCY, super::SPI_BAUD_RATE_FREQUENCY);

board/src/imxrt1170evk-cm7.rs

@@ -92,8 +92,9 @@ pub type SpiPins = hal::lpspi::Pins<
     iomuxc::gpio_ad::GPIO_AD_30, // SDO, J10_8
     iomuxc::gpio_ad::GPIO_AD_31, // SDI, J10_10
     iomuxc::gpio_ad::GPIO_AD_28, // SCK, J10_12
-    iomuxc::gpio_ad::GPIO_AD_29, // PCS0, J10_6
 >;
+/// SPI PCS0 (J10_6).
+pub type SpiPcs0 = iomuxc::gpio_ad::GPIO_AD_29;
 const SPI_INSTANCE: u8 = 1;
 
 #[cfg(feature = "spi")]
@@ -207,8 +208,11 @@ impl Specifics {
                 sdo: iomuxc.gpio_ad.p30,
                 sdi: iomuxc.gpio_ad.p31,
                 sck: iomuxc.gpio_ad.p28,
-                pcs0: iomuxc.gpio_ad.p29,
             };
+            crate::iomuxc::lpspi::prepare({
+                let pcs0: &mut SpiPcs0 = &mut iomuxc.gpio_ad.p29;
+                pcs0
+            });
             let mut spi = Spi::new(lpspi1, pins);
             spi.disabled(|spi| {
                 spi.set_clock_hz(LPSPI_CLK_FREQUENCY, super::SPI_BAUD_RATE_FREQUENCY);

board/src/teensy4.rs

@@ -49,9 +49,11 @@ pub type SpiPins = hal::lpspi::Pins<
     iomuxc::gpio_b0::GPIO_B0_02, // SDO, P11
     iomuxc::gpio_b0::GPIO_B0_01, // SDI, P12
     iomuxc::gpio_b0::GPIO_B0_03, // SCK, P13
-    iomuxc::gpio_b0::GPIO_B0_00, // PCS0, P10
 >;
 
+/// SPI PCS0 (P10).
+pub type SpiPcs0 = iomuxc::gpio_b0::GPIO_B0_00;
+
 #[cfg(not(feature = "spi"))]
 /// Activate the `"spi"` feature to configure the SPI peripheral.
 pub type Spi = ();
@@ -152,8 +154,11 @@ impl Specifics {
                 sdo: iomuxc.gpio_b0.p02,
                 sdi: iomuxc.gpio_b0.p01,
                 sck: iomuxc.gpio_b0.p03,
-                pcs0: iomuxc.gpio_b0.p00,
             };
+            crate::iomuxc::lpspi::prepare({
+                let pcs0: &mut SpiPcs0 = &mut iomuxc.gpio_b0.p00;
+                pcs0
+            });
             let mut spi = Spi::new(lpspi4, pins);
             spi.disabled(|spi| {
                 spi.set_clock_hz(super::LPSPI_CLK_FREQUENCY, super::SPI_BAUD_RATE_FREQUENCY);

src/chip/drivers/dma.rs

@@ -196,10 +196,9 @@ impl<P, const N: u8> lpspi::Lpspi<P, N> {
         channel: &'a mut Channel,
         buffer: &'a [u32],
     ) -> Result<peripheral::Write<'a, Self, u32>, lpspi::LpspiError> {
-        let mut transaction = lpspi::Transaction::new_u32s(buffer)?;
-        transaction.bit_order = self.bit_order();
-
+        let mut transaction = self.bus_transaction(buffer)?;
         transaction.receive_data_mask = true;
+
         self.wait_for_transmit_fifo_space()?;
         self.enqueue_transaction(&transaction);
         Ok(peripheral::write(channel, buffer, self))
@@ -216,10 +215,9 @@ impl<P, const N: u8> lpspi::Lpspi<P, N> {
         channel: &'a mut Channel,
         buffer: &'a mut [u32],
     ) -> Result<peripheral::Read<'a, Self, u32>, lpspi::LpspiError> {
-        let mut transaction = lpspi::Transaction::new_u32s(buffer)?;
-        transaction.bit_order = self.bit_order();
-
+        let mut transaction = self.bus_transaction(buffer)?;
         transaction.transmit_data_mask = true;
+
         self.wait_for_transmit_fifo_space()?;
         self.enqueue_transaction(&transaction);
         Ok(peripheral::read(channel, self, buffer))
@@ -238,8 +236,7 @@ impl<P, const N: u8> lpspi::Lpspi<P, N> {
         tx: &'a mut Channel,
         buffer: &'a mut [u32],
     ) -> Result<peripheral::FullDuplex<'a, Self, u32>, lpspi::LpspiError> {
-        let mut transaction = lpspi::Transaction::new_u32s(buffer)?;
-        transaction.bit_order = self.bit_order();
+        let transaction = self.bus_transaction(buffer)?;
 
         self.wait_for_transmit_fifo_space()?;
         self.enqueue_transaction(&transaction);