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kdave committed Sep 7, 2024
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4 changes: 4 additions & 0 deletions .mailmap
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Expand Up @@ -269,6 +269,7 @@ James Ketrenos <jketreno@io.(none)>
Jan Glauber <jan.glauber@gmail.com> <jang@de.ibm.com>
Jan Glauber <jan.glauber@gmail.com> <jang@linux.vnet.ibm.com>
Jan Glauber <jan.glauber@gmail.com> <jglauber@cavium.com>
Jan Kuliga <jtkuliga.kdev@gmail.com> <jankul@alatek.krakow.pl>
Jarkko Sakkinen <jarkko@kernel.org> <jarkko.sakkinen@linux.intel.com>
Jarkko Sakkinen <jarkko@kernel.org> <jarkko@profian.com>
Jarkko Sakkinen <jarkko@kernel.org> <jarkko.sakkinen@tuni.fi>
Expand Down Expand Up @@ -354,6 +355,8 @@ Kenneth Westfield <quic_kwestfie@quicinc.com> <kwestfie@codeaurora.org>
Kiran Gunda <quic_kgunda@quicinc.com> <kgunda@codeaurora.org>
Kirill Tkhai <tkhai@ya.ru> <ktkhai@virtuozzo.com>
Kishon Vijay Abraham I <kishon@kernel.org> <kishon@ti.com>
Konrad Dybcio <konradybcio@kernel.org> <konrad.dybcio@linaro.org>
Konrad Dybcio <konradybcio@kernel.org> <konrad.dybcio@somainline.org>
Konstantin Khlebnikov <koct9i@gmail.com> <khlebnikov@yandex-team.ru>
Konstantin Khlebnikov <koct9i@gmail.com> <k.khlebnikov@samsung.com>
Koushik <raghavendra.koushik@neterion.com>
Expand Down Expand Up @@ -614,6 +617,7 @@ Simon Kelley <simon@thekelleys.org.uk>
Sricharan Ramabadhran <quic_srichara@quicinc.com> <sricharan@codeaurora.org>
Srinivas Ramana <quic_sramana@quicinc.com> <sramana@codeaurora.org>
Sriram R <quic_srirrama@quicinc.com> <srirrama@codeaurora.org>
Sriram Yagnaraman <sriram.yagnaraman@ericsson.com> <sriram.yagnaraman@est.tech>
Stanislav Fomichev <sdf@fomichev.me> <sdf@google.com>
Stefan Wahren <wahrenst@gmx.net> <stefan.wahren@i2se.com>
Stéphane Witzmann <stephane.witzmann@ubpmes.univ-bpclermont.fr>
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3 changes: 2 additions & 1 deletion Documentation/ABI/testing/sysfs-devices-system-cpu
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Expand Up @@ -562,7 +562,8 @@ Description: Control Symmetric Multi Threading (SMT)
================ =========================================

If control status is "forceoff" or "notsupported" writes
are rejected.
are rejected. Note that enabling SMT on PowerPC skips
offline cores.

What: /sys/devices/system/cpu/cpuX/power/energy_perf_bias
Date: March 2019
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7 changes: 4 additions & 3 deletions Documentation/admin-guide/cgroup-v2.rst
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Expand Up @@ -1717,9 +1717,10 @@ The following nested keys are defined.
entries fault back in or are written out to disk.

memory.zswap.writeback
A read-write single value file. The default value is "1". The
initial value of the root cgroup is 1, and when a new cgroup is
created, it inherits the current value of its parent.
A read-write single value file. The default value is "1".
Note that this setting is hierarchical, i.e. the writeback would be
implicitly disabled for child cgroups if the upper hierarchy
does so.

When this is set to 0, all swapping attempts to swapping devices
are disabled. This included both zswap writebacks, and swapping due
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15 changes: 8 additions & 7 deletions Documentation/admin-guide/device-mapper/dm-crypt.rst
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Expand Up @@ -162,13 +162,14 @@ iv_large_sectors


Module parameters::
max_read_size
max_write_size
Maximum size of read or write requests. When a request larger than this size
is received, dm-crypt will split the request. The splitting improves
concurrency (the split requests could be encrypted in parallel by multiple
cores), but it also causes overhead. The user should tune these parameters to
fit the actual workload.

max_read_size
max_write_size
Maximum size of read or write requests. When a request larger than this size
is received, dm-crypt will split the request. The splitting improves
concurrency (the split requests could be encrypted in parallel by multiple
cores), but it also causes overhead. The user should tune these parameters to
fit the actual workload.


Example scripts
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36 changes: 22 additions & 14 deletions Documentation/arch/riscv/hwprobe.rst
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Expand Up @@ -239,25 +239,33 @@ The following keys are defined:
ratified in commit 98918c844281 ("Merge pull request #1217 from
riscv/zawrs") of riscv-isa-manual.

* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
information about the selected set of processors.
* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: Deprecated. Returns similar values to
:c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`, but the key was
mistakenly classified as a bitmask rather than a value.

* :c:macro:`RISCV_HWPROBE_MISALIGNED_UNKNOWN`: The performance of misaligned
accesses is unknown.
* :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`: An enum value describing
the performance of misaligned scalar native word accesses on the selected set
of processors.

* :c:macro:`RISCV_HWPROBE_MISALIGNED_EMULATED`: Misaligned accesses are
emulated via software, either in or below the kernel. These accesses are
always extremely slow.
* :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN`: The performance of
misaligned scalar accesses is unknown.

* :c:macro:`RISCV_HWPROBE_MISALIGNED_SLOW`: Misaligned accesses are slower
than equivalent byte accesses. Misaligned accesses may be supported
directly in hardware, or trapped and emulated by software.
* :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED`: Misaligned scalar
accesses are emulated via software, either in or below the kernel. These
accesses are always extremely slow.

* :c:macro:`RISCV_HWPROBE_MISALIGNED_FAST`: Misaligned accesses are faster
than equivalent byte accesses.
* :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW`: Misaligned scalar native
word sized accesses are slower than the equivalent quantity of byte
accesses. Misaligned accesses may be supported directly in hardware, or
trapped and emulated by software.

* :c:macro:`RISCV_HWPROBE_MISALIGNED_UNSUPPORTED`: Misaligned accesses are
not supported at all and will generate a misaligned address fault.
* :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_FAST`: Misaligned scalar native
word sized accesses are faster than the equivalent quantity of byte
accesses.

* :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_UNSUPPORTED`: Misaligned scalar
accesses are not supported at all and will generate a misaligned address
fault.

* :c:macro:`RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE`: An unsigned int which
represents the size of the Zicboz block in bytes.
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2 changes: 1 addition & 1 deletion Documentation/core-api/workqueue.rst
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Expand Up @@ -260,7 +260,7 @@ Some users depend on strict execution ordering where only one work item
is in flight at any given time and the work items are processed in
queueing order. While the combination of ``@max_active`` of 1 and
``WQ_UNBOUND`` used to achieve this behavior, this is no longer the
case. Use ``alloc_ordered_queue()`` instead.
case. Use alloc_ordered_workqueue() instead.


Example Execution Scenarios
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2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/clock/qcom,dispcc-sm6350.yaml
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Expand Up @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock & Reset Controller on SM6350

maintainers:
- Konrad Dybcio <konrad.dybcio@somainline.org>
- Konrad Dybcio <konradybcio@kernel.org>

description: |
Qualcomm display clock control module provides the clocks, resets and power
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2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml
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Expand Up @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on MSM8994

maintainers:
- Konrad Dybcio <konrad.dybcio@somainline.org>
- Konrad Dybcio <konradybcio@kernel.org>

description: |
Qualcomm global clock control module provides the clocks, resets and power
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2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/clock/qcom,gcc-sm6125.yaml
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Expand Up @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on SM6125

maintainers:
- Konrad Dybcio <konrad.dybcio@somainline.org>
- Konrad Dybcio <konradybcio@kernel.org>

description: |
Qualcomm global clock control module provides the clocks, resets and power
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2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/clock/qcom,gcc-sm6350.yaml
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Expand Up @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on SM6350

maintainers:
- Konrad Dybcio <konrad.dybcio@somainline.org>
- Konrad Dybcio <konradybcio@kernel.org>

description: |
Qualcomm global clock control module provides the clocks, resets and power
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2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml
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Expand Up @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Graphics Clock & Reset Controller on SM6115

maintainers:
- Konrad Dybcio <konrad.dybcio@linaro.org>
- Konrad Dybcio <konradybcio@kernel.org>

description: |
Qualcomm graphics clock control module provides clocks, resets and power
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2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/clock/qcom,sm6125-gpucc.yaml
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Expand Up @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Graphics Clock & Reset Controller on SM6125

maintainers:
- Konrad Dybcio <konrad.dybcio@linaro.org>
- Konrad Dybcio <konradybcio@kernel.org>

description: |
Qualcomm graphics clock control module provides clocks and power domains on
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2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/clock/qcom,sm6350-camcc.yaml
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Expand Up @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Camera Clock & Reset Controller on SM6350

maintainers:
- Konrad Dybcio <konrad.dybcio@linaro.org>
- Konrad Dybcio <konradybcio@kernel.org>

description: |
Qualcomm camera clock control module provides the clocks, resets and power
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2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/clock/qcom,sm6375-dispcc.yaml
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Expand Up @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock & Reset Controller on SM6375

maintainers:
- Konrad Dybcio <konrad.dybcio@linaro.org>
- Konrad Dybcio <konradybcio@kernel.org>

description: |
Qualcomm display clock control module provides the clocks, resets and power
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2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/clock/qcom,sm6375-gcc.yaml
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Expand Up @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on SM6375

maintainers:
- Konrad Dybcio <konrad.dybcio@somainline.org>
- Konrad Dybcio <konradybcio@kernel.org>

description: |
Qualcomm global clock control module provides the clocks, resets and power
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2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml
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Expand Up @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Graphics Clock & Reset Controller on SM6375

maintainers:
- Konrad Dybcio <konrad.dybcio@linaro.org>
- Konrad Dybcio <konradybcio@kernel.org>

description: |
Qualcomm graphics clock control module provides clocks, resets and power
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2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/clock/qcom,sm8350-videocc.yaml
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Expand Up @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SM8350 Video Clock & Reset Controller

maintainers:
- Konrad Dybcio <konrad.dybcio@linaro.org>
- Konrad Dybcio <konradybcio@kernel.org>

description: |
Qualcomm video clock control module provides the clocks, resets and power
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2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml
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Expand Up @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Graphics Clock & Reset Controller on SM8450

maintainers:
- Konrad Dybcio <konrad.dybcio@linaro.org>
- Konrad Dybcio <konradybcio@kernel.org>

description: |
Qualcomm graphics clock control module provides the clocks, resets and power
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2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml
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Expand Up @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SM6375 Display MDSS

maintainers:
- Konrad Dybcio <konrad.dybcio@linaro.org>
- Konrad Dybcio <konradybcio@kernel.org>

description:
SM6375 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
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2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/display/panel/asus,z00t-tm5p5-nt35596.yaml
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Expand Up @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: ASUS Z00T TM5P5 NT35596 5.5" 1080×1920 LCD Panel

maintainers:
- Konrad Dybcio <konradybcio@gmail.com>
- Konrad Dybcio <konradybcio@kernel.org>

description: |+
This panel seems to only be found in the Asus Z00T
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12 changes: 6 additions & 6 deletions Documentation/devicetree/bindings/display/panel/samsung,atna33xc20.yaml
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Expand Up @@ -18,12 +18,12 @@ properties:
# Samsung 13.3" FHD (1920x1080 pixels) eDP AMOLED panel
- const: samsung,atna33xc20
- items:
- enum:
# Samsung 14.5" WQXGA+ (2880x1800 pixels) eDP AMOLED panel
- samsung,atna45af01
# Samsung 14.5" 3K (2944x1840 pixels) eDP AMOLED panel
- samsung,atna45dc02
- const: samsung,atna33xc20
- enum:
# Samsung 14.5" WQXGA+ (2880x1800 pixels) eDP AMOLED panel
- samsung,atna45af01
# Samsung 14.5" 3K (2944x1840 pixels) eDP AMOLED panel
- samsung,atna45dc02
- const: samsung,atna33xc20

enable-gpios: true
port: true
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2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/display/panel/sony,td4353-jdi.yaml
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Expand Up @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Sony TD4353 JDI 5 / 5.7" 2160x1080 MIPI-DSI Panel

maintainers:
- Konrad Dybcio <konrad.dybcio@somainline.org>
- Konrad Dybcio <konradybcio@kernel.org>

description: |
The Sony TD4353 JDI is a 5 (XZ2c) / 5.7 (XZ2) inch 2160x1080
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1 change: 1 addition & 0 deletions Documentation/devicetree/bindings/eeprom/at25.yaml
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Expand Up @@ -28,6 +28,7 @@ properties:
- anvo,anv32e61w
- atmel,at25256B
- fujitsu,mb85rs1mt
- fujitsu,mb85rs256
- fujitsu,mb85rs64
- microchip,at25160bn
- microchip,25lc040
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1 change: 1 addition & 0 deletions Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.yaml
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Expand Up @@ -42,6 +42,7 @@ properties:
- focaltech,ft5426
- focaltech,ft5452
- focaltech,ft6236
- focaltech,ft8201
- focaltech,ft8719

reg:
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2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/interconnect/qcom,sc7280-rpmh.yaml
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Expand Up @@ -8,7 +8,7 @@ title: Qualcomm RPMh Network-On-Chip Interconnect on SC7280

maintainers:
- Bjorn Andersson <andersson@kernel.org>
- Konrad Dybcio <konrad.dybcio@linaro.org>
- Konrad Dybcio <konradybcio@kernel.org>

description: |
RPMh interconnect providers support system bandwidth requirements through
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2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/interconnect/qcom,sc8280xp-rpmh.yaml
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Expand Up @@ -8,7 +8,7 @@ title: Qualcomm RPMh Network-On-Chip Interconnect on SC8280XP

maintainers:
- Bjorn Andersson <andersson@kernel.org>
- Konrad Dybcio <konrad.dybcio@linaro.org>
- Konrad Dybcio <konradybcio@kernel.org>

description: |
RPMh interconnect providers support system bandwidth requirements through
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2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/interconnect/qcom,sm8450-rpmh.yaml
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Expand Up @@ -8,7 +8,7 @@ title: Qualcomm RPMh Network-On-Chip Interconnect on SM8450

maintainers:
- Bjorn Andersson <andersson@kernel.org>
- Konrad Dybcio <konrad.dybcio@linaro.org>
- Konrad Dybcio <konradybcio@kernel.org>

description: |
RPMh interconnect providers support system bandwidth requirements through
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2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/iommu/qcom,iommu.yaml
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Expand Up @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies legacy IOMMU implementations

maintainers:
- Konrad Dybcio <konrad.dybcio@linaro.org>
- Konrad Dybcio <konradybcio@kernel.org>

description: |
Qualcomm "B" family devices which are not compatible with arm-smmu have
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4 changes: 4 additions & 0 deletions Documentation/devicetree/bindings/net/fsl,qoriq-mc-dpmac.yaml
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Expand Up @@ -38,6 +38,10 @@ properties:

managed: true

phys:
description: A reference to the SerDes lane(s)
maxItems: 1

required:
- reg

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2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/pinctrl/qcom,mdm9607-tlmm.yaml
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Expand Up @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. MDM9607 TLMM block

maintainers:
- Konrad Dybcio <konrad.dybcio@somainline.org>
- Konrad Dybcio <konradybcio@kernel.org>

description:
Top Level Mode Multiplexer pin controller in Qualcomm MDM9607 SoC.
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2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/pinctrl/qcom,sm6350-tlmm.yaml
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Expand Up @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. SM6350 TLMM block

maintainers:
- Konrad Dybcio <konrad.dybcio@somainline.org>
- Konrad Dybcio <konradybcio@kernel.org>

description:
Top Level Mode Multiplexer pin controller in Qualcomm SM6350 SoC.
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2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/pinctrl/qcom,sm6375-tlmm.yaml
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Expand Up @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. SM6375 TLMM block

maintainers:
- Konrad Dybcio <konrad.dybcio@somainline.org>
- Konrad Dybcio <konradybcio@kernel.org>

description:
Top Level Mode Multiplexer pin controller in Qualcomm SM6375 SoC.
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2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/remoteproc/qcom,rpm-proc.yaml
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Expand Up @@ -8,7 +8,7 @@ title: Qualcomm Resource Power Manager (RPM) Processor/Subsystem

maintainers:
- Bjorn Andersson <andersson@kernel.org>
- Konrad Dybcio <konrad.dybcio@linaro.org>
- Konrad Dybcio <konradybcio@kernel.org>
- Stephan Gerhold <stephan@gerhold.net>

description: |
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2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/soc/qcom/qcom,rpm-master-stats.yaml
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Expand Up @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. (QTI) RPM Master Stats

maintainers:
- Konrad Dybcio <konrad.dybcio@linaro.org>
- Konrad Dybcio <konradybcio@kernel.org>

description: |
The Qualcomm RPM (Resource Power Manager) architecture includes a concept
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