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ARM: dts: msm: Update cpuss dump sizes for Atoll
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Update cpuss dump size to match the one required for dump data
collection on Atoll SoC. While at it, add the llcc dump node to
allocate memory for llcc cache dump.

Change-Id: Ie846a6d1b2ca08e82206d12fa3dcce4ea51fd64e
Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>
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Srinivas Ramana authored and Gerrit - the friendly Code Review server committed Aug 19, 2019
1 parent 1d6abc2 commit d846bb2
Showing 1 changed file with 19 additions and 14 deletions.
33 changes: 19 additions & 14 deletions arch/arm64/boot/dts/qcom/atoll.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -74,7 +74,7 @@

L1_I_0: l1-icache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x8800>;
qcom,dump-size = <0x10800>;
};

L1_D_0: l1-dcache {
Expand All @@ -83,7 +83,7 @@
};

L2_TLB_0: l2-tlb {
qcom,dump-size = <0x5000>;
qcom,dump-size = <0x5a00>;
};
};

Expand All @@ -108,7 +108,7 @@

L1_I_100: l1-icache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x8800>;
qcom,dump-size = <0x10800>;
};

L1_D_100: l1-dcache {
Expand All @@ -117,7 +117,7 @@
};

L2_TLB_100: l2-tlb {
qcom,dump-size = <0x5000>;
qcom,dump-size = <0x5a00>;
};
};

Expand All @@ -143,7 +143,7 @@

L1_I_200: l1-icache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x8800>;
qcom,dump-size = <0x10800>;
};

L1_D_200: l1-dcache {
Expand All @@ -152,7 +152,7 @@
};

L2_TLB_200: l2-tlb {
qcom,dump-size = <0x5000>;
qcom,dump-size = <0x5a00>;
};
};

Expand All @@ -177,7 +177,7 @@

L1_I_300: l1-icache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x8800>;
qcom,dump-size = <0x10800>;
};

L1_D_300: l1-dcache {
Expand All @@ -186,7 +186,7 @@
};

L2_TLB_300: l2-tlb {
qcom,dump-size = <0x5000>;
qcom,dump-size = <0x5a00>;
};
};

Expand All @@ -211,7 +211,7 @@

L1_I_400: l1-icache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x8800>;
qcom,dump-size = <0x10800>;
};

L1_D_400: l1-dcache {
Expand All @@ -220,7 +220,7 @@
};

L2_TLB_400: l2-tlb {
qcom,dump-size = <0x5000>;
qcom,dump-size = <0x5a00>;
};
};

Expand All @@ -245,7 +245,7 @@

L1_I_500: l1-icache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x8800>;
qcom,dump-size = <0x10800>;
};

L1_D_500: l1-dcache {
Expand All @@ -254,7 +254,7 @@
};

L2_TLB_500: l2-tlb {
qcom,dump-size = <0x5000>;
qcom,dump-size = <0x5a00>;
};
};

Expand All @@ -280,7 +280,7 @@

L1_I_600: l1-icache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x11000>;
qcom,dump-size = <0x22000>;
};

L1_D_600: l1-dcache {
Expand Down Expand Up @@ -323,7 +323,7 @@

L1_I_700: l1-icache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x11000>;
qcom,dump-size = <0x22000>;
};

L1_D_700: l1-dcache {
Expand Down Expand Up @@ -1542,6 +1542,11 @@
qcom,dump-node = <&L2_TLB_700>;
qcom,dump-id = <0x127>;
};

qcom,llcc1_d_cache {
qcom,dump-node = <&LLCC_1>;
qcom,dump-id = <0x140>;
};
};

mem_dump {
Expand Down

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