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Enable XSAVE feature in CPUID #472
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Access to extended control register requires XGETBV and XSETBV instructions support. In order to add the support for the extended control register, encapsulate these two instructions. * Add unified interfaces ia32_xgetbv() and ia32_xsetbv() for 32-bit and 64-bit platforms * Implement assembly functions asm_xgetbv() and asm_xsetbv() to encapsulate XGETBV and XSETBV instructions respectively Signed-off-by: Wenchao Wang <wenchao.wang@intel.com>
Introduce extended control register XCR0 to support XSAVE feature set. A new header file for FPU (Floating-Point Unit) is introduced. * Add XCR0 variables for both CPU states of host and guest * Define the feature bits in XCR0 supported by HAXM * Initialize XCR0 states for both host and guest Signed-off-by: Wenchao Wang <wenchao.wang@intel.com>
Since HAXM only supports part of the XCR0 feature bits, the XCR0 values of guest and host will be inconsistent. Therefore, guest XCR0 and host XCR0 will be loaded respectively during VM entry and VM exit. * Add complete bits definition for CR4 * Add implementation to load guest XSAVE state before VM entry * Add implementation to load host XSAVE state after VM exit Signed-off-by: Wenchao Wang <wenchao.wang@intel.com>
Enable XSAVE related instructions except XSAVES, and calculate size in bytes of the XSAVE area required by enabled features in XCR0. * Add x86 features definition for CPUID.(EAX=0DH,ECX=1).EAX * Add execute() function of CPUID.0DH and cache the values of sub-leaf 0 and 1 of CPUID.0DH * Implement the function for calculating XSTATE required size Signed-off-by: Wenchao Wang <wenchao.wang@intel.com>
CPUID.(EAX=0DH,ECX=0) is responsible for reporting the settable XCR0 feature bits (see Intel SDM Vol. 2A 3.2 CPUID). Add the valid_xcr0 variable to store this CPUID result of guest. As all VCPUs in the same VM share the same CPUID in HAXM, this variable is placed in the space of VM. * Implement a function that calculates the XCR0 feature bits that can be set by guest * After initializing CPUID and setting CPUID by user, calculate the value of valid_xcr0 Signed-off-by: Wenchao Wang <wenchao.wang@intel.com>
Reading and writing of XCR is performed by XGETBV and XSETBV instructions. By intercepting VM exit caused by the guest executing XSETBV instruction, the XCR value to be set by the guest can be recorded. Currently HAXM only supports XCR0. It ensures that XCR0 of the guest and XCR0 of the VCPU in HAXM are synchronized, and the value of XCR0 can be loaded correctly during VM entry. * Implement the interception of the VM exit caused by the guest executing XSETBV instruction * Implement functions to set and get VCPU XCR Signed-off-by: Wenchao Wang <wenchao.wang@intel.com>
When certain state bits of VCPU registers change, the guest CPUID results associated with them also need to be updated accordingly. * Implement the function to update CPUID. Refresh all CPUIDs that may be impacted. * Update CPUIDs when the below guest register state bits change: - CR4_OSXSAVE in CR4 - Any bit of XFEATURE_MASK_EXTENDED in XCR0 Signed-off-by: Wenchao Wang <wenchao.wang@intel.com>
Enable X86_FEATURE_XSAVE support in CPUID. Since Android 10.0 (API 29) system images enabled AVX feature, which requires XSAVE support (see Intel SDM Vol. 1: 13.1 XSAVE-Supported Features and State-Component Bitmaps). When both XSAVE and AVX are enabled, the above system images can be booted normally. Signed-off-by: Wenchao Wang <wenchao.wang@intel.com>
hyuan3
approved these changes
Oct 18, 2022
hyuan3
approved these changes
Oct 18, 2022
hyuan3
approved these changes
Oct 18, 2022
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The XSAVE feature set extends the functionality of the FXSAVE and FXRSTOR instructions (see Intel SDM Vol. 1: 13 Managing State using the XSAVE Feature Set). Some current features, such as AVX, will only work properly if the XSAVE feature is enabled.
Enabling XSAVE feature allows the guest OS with AVX (or other XSAVE-supported features) enabled can boot normally.