drm/i915/gt: SR-IOV feature enablement

This SR-IOV feature based on DII_5299

Signed-off-by: Zawawi, Muhammad Zul Husni <muhammad.zul.husni.zawawi@intel.com>

Documentation/gpu/i915.rst

@@ -541,6 +541,22 @@ GuC ABI
 .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
 .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h
 
+GuC Virtualization ABI
+~~~~~~~~~~~~~~~~~~~~~~
+
+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_actions_pf_abi.h
+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_actions_vf_abi.h
+
+GuC VF/PF Virtualization ABI
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. kernel-doc:: drivers/gpu/drm/i915/gt/iov/abi/iov_communication_abi.h
+.. kernel-doc:: drivers/gpu/drm/i915/gt/iov/abi/iov_communication_mmio_abi.h
+.. kernel-doc:: drivers/gpu/drm/i915/gt/iov/abi/iov_messages_abi.h
+.. kernel-doc:: drivers/gpu/drm/i915/gt/iov/abi/iov_actions_abi.h
+.. kernel-doc:: drivers/gpu/drm/i915/gt/iov/abi/iov_actions_mmio_abi.h
+.. kernel-doc:: drivers/gpu/drm/i915/gt/iov/abi/iov_errors_abi.h
+
 HuC
 ---
 .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c

drivers/gpu/drm/i915/Kconfig.debug

@@ -167,6 +167,18 @@ config DRM_I915_DEBUG_GUC
 
 	  If in doubt, say "N".
 
+config DRM_I915_DEBUG_IOV
+	bool "Enable additional driver debugging for IOV"
+	depends on DRM_I915
+	default n
+	help
+	  Choose this option to turn on extra driver debugging that may affect
+	  performance but will help resolve IOV related issues.
+
+	  Recommended for driver developers only.
+
+	  If in doubt, say "N".
+
 config DRM_I915_SELFTEST
 	bool "Enable selftests upon driver load"
 	depends on DRM_I915

drivers/gpu/drm/i915/Makefile

@@ -198,6 +198,25 @@ i915-y += gt/uc/intel_uc.o \
 	  gt/uc/intel_huc_debugfs.o \
 	  gt/uc/intel_huc_fw.o
 
+# Virtualization support
+iov-y += \
+	i915_sriov.o \
+	i915_sriov_sysfs.o \
+	gt/iov/intel_iov.o \
+	gt/iov/intel_iov_debugfs.o \
+	gt/iov/intel_iov_event.o \
+	gt/iov/intel_iov_provisioning.o \
+	gt/iov/intel_iov_query.o \
+	gt/iov/intel_iov_relay.o \
+	gt/iov/intel_iov_service.o \
+	gt/iov/intel_iov_state.o \
+	gt/iov/intel_iov_sysfs.o
+i915-y += $(iov-y)
+
+iov-$(CONFIG_DRM_I915_SELFTEST) += \
+	gt/iov/selftests/iov_selftest_actions.o
+i915-y += $(iov-$(CONFIG_DRM_I915_SELFTEST))
+
 # modesetting core code
 i915-y += \
 	display/intel_atomic.o \

drivers/gpu/drm/i915/README.sriov

@@ -0,0 +1,6 @@
+BEGIN SR-IOV ENABLING
+D:	Michal Wajdeczko <michal.wajdeczko@intel.com>
+M:	Michal Wajdeczko <michal.wajdeczko@intel.com>
+T:	drm/i915/iov
+T:	drm/i915/pf
+END TGL

drivers/gpu/drm/i915/display/intel_display_power.c

@@ -5264,6 +5264,23 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
 	return err;
 }
 
+/**
+ * intel_power_domains_prune - prunes the power domain structures
+ * @dev_priv: i915 device instance
+ *
+ * We might have detected that power domain initialization done earlier
+ * requires some additional tweaks.
+ */
+void intel_power_domains_prune(struct drm_i915_private *dev_priv)
+{
+	struct i915_power_domains *power_domains = &dev_priv->power_domains;
+
+	if (IS_SRIOV_VF(dev_priv)) {
+		set_power_wells(power_domains, i9xx_always_on_power_well);
+		return;
+	}
+}
+
 /**
  * intel_power_domains_cleanup - clean up power domains resources
  * @dev_priv: i915 device instance

drivers/gpu/drm/i915/display/intel_display_power.h

@@ -211,6 +211,7 @@ struct intel_display_power_domain_set {
 		for_each_if((__power_well)->desc->domains & (__domain_mask))
 
 int intel_power_domains_init(struct drm_i915_private *dev_priv);
+void intel_power_domains_prune(struct drm_i915_private *dev_priv);
 void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
 void intel_power_domains_driver_remove(struct drm_i915_private *dev_priv);

drivers/gpu/drm/i915/display/intel_dpt.c

@@ -29,11 +29,6 @@ i915_vm_to_dpt(struct i915_address_space *vm)
 
 #define dpt_total_entries(dpt) ((dpt)->vm.total >> PAGE_SHIFT)
 
-static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
-{
-	writeq(pte, addr);
-}
-
 static void dpt_insert_page(struct i915_address_space *vm,
 			    dma_addr_t addr,
 			    u64 offset,

drivers/gpu/drm/i915/display/intel_opregion.c

@@ -868,6 +868,9 @@ int intel_opregion_setup(struct drm_i915_private *dev_priv)
 	BUILD_BUG_ON(sizeof(struct opregion_asle) != 0x100);
 	BUILD_BUG_ON(sizeof(struct opregion_asle_ext) != 0x400);
 
+	if (IS_SRIOV_VF(dev_priv))
+		return 0;
+
 	pci_read_config_dword(pdev, ASLS, &asls);
 	drm_dbg(&dev_priv->drm, "graphic opregion physical addr: 0x%x\n",
 		asls);

drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c

@@ -3335,12 +3335,17 @@ i915_gem_do_execbuffer(struct drm_device *dev,
 
 	eb.batch_flags = 0;
 	if (args->flags & I915_EXEC_SECURE) {
-		if (GRAPHICS_VER(i915) >= 11)
-			return -ENODEV;
+		if (!i915->params.enable_secure_batch) {
+			if (GRAPHICS_VER(i915) >= 11)
+				return -ENODEV;
 
-		/* Return -EPERM to trigger fallback code on old binaries. */
-		if (!HAS_SECURE_BATCHES(i915))
-			return -EPERM;
+			/*
+			 * Return -EPERM to trigger fallback code on old
+			 * binaries.
+			 */
+			if (!HAS_SECURE_BATCHES(i915))
+				return -EPERM;
+		}
 
 		if (!drm_is_current_master(file) || !capable(CAP_SYS_ADMIN))
 			return -EPERM;

drivers/gpu/drm/i915/gt/intel_engine_cs.c

@@ -296,6 +296,9 @@ static void __sprint_engine_name(struct intel_engine_cs *engine)
 
 void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask)
 {
+	if (IS_SRIOV_VF(engine->i915))
+		return;
+
 	/*
 	 * Though they added more rings on g4x/ilk, they did not add
 	 * per-engine HWSTAM until gen6.
@@ -1635,6 +1638,10 @@ static void intel_engine_print_registers(struct intel_engine_cs *engine,
 	struct intel_engine_execlists * const execlists = &engine->execlists;
 	u64 addr;
 
+	/* VF can't access these registers */
+	if (IS_SRIOV_VF(dev_priv))
+		return;
+
 	if (engine->id == RENDER_CLASS && IS_GRAPHICS_VER(dev_priv, 4, 7))
 		drm_printf(m, "\tCCID: 0x%08x\n", ENGINE_READ(engine, CCID));
 	if (HAS_EXECLISTS(dev_priv)) {