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[SYCL] Support memory clock rate and memory bus width queries #7412

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merged 7 commits into from
Nov 17, 2022

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againull
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@againull againull commented Nov 16, 2022

@againull againull requested review from a team as code owners November 16, 2022 07:51
@againull againull changed the title [SYCL] Support memory clock rate and memory bus width properties [SYCL] Support memory clock rate and memory bus width queries Nov 16, 2022
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@gmlueck gmlueck left a comment

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Spec change LGTM

sycl/plugins/level_zero/pi_level_zero.cpp Outdated Show resolved Hide resolved
sycl/plugins/level_zero/pi_level_zero.cpp Outdated Show resolved Hide resolved
sycl/unittests/kernel-and-program/DeviceInfo.cpp Outdated Show resolved Hide resolved
@@ -3180,7 +3180,40 @@ pi_result piDeviceGetInfo(pi_device Device, pi_device_info ParamName,
}
return ReturnValue(FreeMemory);
}
case PI_EXT_INTEL_DEVICE_INFO_MEMORY_CLOCK_RATE: {
// If there are no any memory modules then return 0.
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Let's document this behavior in pi.h

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And in the .md too, and also explain what is returned when a device has multiple memories

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Updated pi.h and document.


# Memory Clock Rate #

A new device descriptor will be added which will provide the maximum clock rate of device's global memory.
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Suggested change
A new device descriptor will be added which will provide the maximum clock rate of device's global memory.
A new device descriptor is added which provides the maximum clock rate of device's global memory.

?

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Fixed.

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@smaslov-intel smaslov-intel left a comment

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LGTM. Just a few documentation asks

@againull againull requested a review from a team as a code owner November 16, 2022 20:14
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@steffenlarsen steffenlarsen left a comment

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LGTM!

@steffenlarsen steffenlarsen merged commit 4f7787c into intel:sycl Nov 17, 2022
@againull againull deleted the clock_rate_and_bus_width branch December 2, 2022 23:23
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4 participants