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adding "bottleneck" string where applicable to metric names in metric…
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@1perrytaylor
1perrytaylor committed Nov 27, 2024
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6 changes: 3 additions & 3 deletions ADL/metrics/alderlake_metrics_goldencove_core.json
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6 changes: 3 additions & 3 deletions ADL/metrics/perf/alderlake_metrics_goldencove_core_perf.json
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Expand Up @@ -20,7 +20,7 @@
},
{
"BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks (when the front-end could not sustain operations delivery to the back-end)",
"MetricExpr": "100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( 1 - INST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.MS\\,cmask\\=0x1@ ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_lsd + tma_ms ) ) ) ) - tma_big_code",
"MetricExpr": "100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( 1 - INST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.MS\\,cmask\\=0x1@ ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_lsd + tma_ms ) ) ) ) - tma_bottleneck_big_code",
"MetricGroup": "BvFB;Fed;FetchBW;Frontend;TopdownL1;tma_L1_group;Default;Scaled_Slots",
"MetricName": "tma_bottleneck_instruction_fetch_bw",
"MetricThreshold": "tma_bottleneck_instruction_fetch_bw > 20",
Expand Down Expand Up @@ -89,7 +89,7 @@
},
{
"BriefDescription": "Total pipeline cost of remaining bottlenecks in the back-end",
"MetricExpr": "100 - ( tma_big_code + tma_instruction_fetch_bw + tma_mispredictions + tma_cache_memory_bandwidth + tma_cache_memory_latency + tma_memory_data_tlbs + tma_memory_synchronization + tma_compute_bound_est + tma_irregular_overhead + tma_branching_overhead + tma_useful_work )",
"MetricExpr": "100 - ( tma_bottleneck_big_code + tma_bottleneck_instruction_fetch_bw + tma_bottleneck_mispredictions + tma_bottleneck_cache_memory_bandwidth + ma_bottleneck_cache_memory_latency + tma_bottleneck_memory_data_tlbs + tma_bottleneck_memory_synchronization + tma_bottleneck_compute_bound_est + tma_bottleneck_irregular_overhead + tma_bottleneck_branching_overhead + tma_bottleneck_useful_work )",
"MetricGroup": "BvOB;Cor;Offcore;TopdownL1;tma_L1_group;Default;Scaled_Slots",
"MetricName": "tma_bottleneck_other_bottlenecks",
"MetricThreshold": "tma_bottleneck_other_bottlenecks > 20",
Expand Down Expand Up @@ -1475,7 +1475,7 @@
},
{
"BriefDescription": "Branch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
"MetricExpr": "tma_mispredictions * tma_info_thread_slots / ( 6 ) / BR_MISP_RETIRED.ALL_BRANCHES / 100",
"MetricExpr": "tma_bottleneck_mispredictions * tma_info_thread_slots / ( 6 ) / BR_MISP_RETIRED.ALL_BRANCHES / 100",
"MetricGroup": "Bad;BrMispredicts;Core_Metric;tma_issueBM",
"MetricName": "tma_info_bad_spec_branch_misprediction_cost",
"PublicDescription": "Branch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear). Related metrics: tma_bottleneck_mispredictions, tma_branch_mispredicts, tma_mispredicts_resteers."
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4 changes: 2 additions & 2 deletions ARL/metrics/arrowlake_metrics_lioncove_core.json
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Expand Up @@ -319,7 +319,7 @@
],
"Constants": [],
"Formula": "100 * ( ( a / ( a + b + c + d ) ) - ( 1 - ( 10 * ( e / ( f ) ) * ( max( ( g / ( a + b + c + d ) ) * ( 1 - h / ( i - j ) ) , 0.0001 ) ) / ( g / ( a + b + c + d ) ) ) ) * ( k / ( a + b + c + d ) ) * ( ( ( g / ( a + b + c + d ) ) / ( b / ( a + b + c + d ) ) ) * l / ( m ) ) / ( ( n / ( m ) ) + ( o / ( m ) ) + ( l / ( m ) + ( p / ( m ) ) ) + ( ( 3 ) * q / ( m ) ) + ( r / ( m ) ) + ( s / ( m ) ) ) - ( ( 1 - t / u ) * ( ( k / ( a + b + c + d ) ) * ( ( ( 3 ) * q / ( m ) ) + ( l / ( m ) + ( p / ( m ) ) ) * ( ( ( 1 - ( ( g / ( a + b + c + d ) ) / ( b / ( a + b + c + d ) ) ) ) * l / ( m ) ) + ( ( ( g / ( a + b + c + d ) ) / ( b / ( a + b + c + d ) ) ) * l / ( m ) ) * ( max( ( g / ( a + b + c + d ) ) * ( 1 - h / ( i - j ) ) , 0.0001 ) ) / ( g / ( a + b + c + d ) ) ) / ( ( ( ( g / ( a + b + c + d ) ) / ( b / ( a + b + c + d ) ) ) * l / ( m ) ) + ( ( 1 - ( ( g / ( a + b + c + d ) ) / ( b / ( a + b + c + d ) ) ) ) * l / ( m ) ) + ( p / ( m ) ) ) ) / ( ( n / ( m ) ) + ( o / ( m ) ) + ( l / ( m ) + ( p / ( m ) ) ) + ( ( 3 ) * q / ( m ) ) + ( r / ( m ) ) + ( s / ( m ) ) ) + ( max( 0 , ( a / ( a + b + c + d ) ) - ( k / ( a + b + c + d ) ) ) ) * ( v / ( m ) ) / ( ( ( w / ( m ) + x / ( y + x ) * ( z - a_a ) ) / ( m ) ) + ( ( a_b + y / ( y + x ) * ( z - a_a ) ) / ( m ) ) + ( a_c / ( m ) ) + ( v / ( m ) ) ) ) ) ) - ( 100 * ( k / ( a + b + c + d ) ) * ( ( o / ( m ) ) + ( n / ( m ) ) + ( p / ( m ) ) ) / ( ( n / ( m ) ) + ( o / ( m ) ) + ( l / ( m ) + ( p / ( m ) ) ) + ( ( 3 ) * q / ( m ) ) + ( r / ( m ) ) + ( s / ( m ) ) ) )",
"BaseFormula": " 100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( 1 - inst_retired.rep_iteration / uops_retired.ms:c1 ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_lsd + tma_ms ) ) ) ) - tma_big_code",
"BaseFormula": " 100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( 1 - inst_retired.rep_iteration / uops_retired.ms:c1 ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_lsd + tma_ms ) ) ) ) - tma_bottleneck_big_code",
"Category": "TMA",
"CountDomain": "Scaled_Slots",
"Threshold": {
Expand Down Expand Up @@ -9171,7 +9171,7 @@
],
"Constants": [],
"Formula": "( 100 * ( 1 - ( 10 * ( a / ( b ) ) * ( max( ( c / ( d + e + f + g ) ) * ( 1 - h / ( i - j ) ) , 0.0001 ) ) / ( c / ( d + e + f + g ) ) ) ) * ( ( c / ( d + e + f + g ) ) + ( k / ( d + e + f + g ) ) * ( ( ( c / ( d + e + f + g ) ) / ( e / ( d + e + f + g ) ) ) * l / ( m ) ) / ( ( n / ( m ) ) + ( o / ( m ) ) + ( l / ( m ) + ( p / ( m ) ) ) + ( ( 3 ) * q / ( m ) ) + ( r / ( m ) ) + ( s / ( m ) ) ) ) ) * ( b ) / ( 8 ) / h / 100",
"BaseFormula": " tma_mispredictions * tma_info_thread_slots / ( 8 ) / br_misp_retired.all_branches / 100",
"BaseFormula": " tma_bottleneck_mispredictions * tma_info_thread_slots / ( 8 ) / br_misp_retired.all_branches / 100",
"Category": "TMA",
"CountDomain": "Core_Metric",
"Threshold": {
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4 changes: 2 additions & 2 deletions ARL/metrics/perf/arrowlake_metrics_lioncove_core_perf.json
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Expand Up @@ -20,7 +20,7 @@
},
{
"BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks (when the front-end could not sustain operations delivery to the back-end)",
"MetricExpr": "100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( 1 - INST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.MS\\,cmask\\=0x1@ ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_lsd + tma_ms ) ) ) ) - tma_big_code",
"MetricExpr": "100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( 1 - INST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.MS\\,cmask\\=0x1@ ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_lsd + tma_ms ) ) ) ) - tma_bottleneck_big_code",
"MetricGroup": "BvFB;Fed;FetchBW;Frontend;TopdownL1;tma_L1_group;Default;Scaled_Slots",
"MetricName": "tma_bottleneck_instruction_fetch_bw",
"MetricThreshold": "tma_bottleneck_instruction_fetch_bw > 20",
Expand Down Expand Up @@ -1440,7 +1440,7 @@
},
{
"BriefDescription": "Branch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
"MetricExpr": "tma_mispredictions * tma_info_thread_slots / ( 8 ) / BR_MISP_RETIRED.ALL_BRANCHES / 100",
"MetricExpr": "tma_bottleneck_mispredictions * tma_info_thread_slots / ( 8 ) / BR_MISP_RETIRED.ALL_BRANCHES / 100",
"MetricGroup": "Bad;BrMispredicts;Core_Metric;tma_issueBM",
"MetricName": "tma_info_bad_spec_branch_misprediction_cost",
"PublicDescription": "Branch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear). Related metrics: tma_bottleneck_mispredictions, tma_branch_mispredicts, tma_mispredicts_resteers."
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6 changes: 3 additions & 3 deletions CLX/metrics/cascadelakex_metrics.json
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6 changes: 3 additions & 3 deletions CLX/metrics/perf/cascadelakex_metrics_perf.json
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Expand Up @@ -315,7 +315,7 @@
},
{
"BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks (when the front-end could not sustain operations delivery to the back-end)",
"MetricExpr": "100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( ( tma_microcode_sequencer / ( tma_few_uops_instructions + tma_microcode_sequencer ) ) * ( tma_assists / tma_microcode_sequencer ) ) * tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) ) ) - tma_big_code",
"MetricExpr": "100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( ( tma_microcode_sequencer / ( tma_few_uops_instructions + tma_microcode_sequencer ) ) * ( tma_assists / tma_microcode_sequencer ) ) * tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) ) ) - tma_bottleneck_big_code",
"MetricGroup": "BvFB;Fed;FetchBW;Frontend;TopdownL1;tma_L1_group;Scaled_Slots",
"MetricName": "tma_bottleneck_instruction_fetch_bw",
"MetricThreshold": "tma_bottleneck_instruction_fetch_bw > 20"
Expand Down Expand Up @@ -370,7 +370,7 @@
},
{
"BriefDescription": "Total pipeline cost of remaining bottlenecks in the back-end",
"MetricExpr": "100 - ( tma_big_code + tma_instruction_fetch_bw + tma_mispredictions + tma_cache_memory_bandwidth + tma_cache_memory_latency + tma_memory_data_tlbs + tma_memory_synchronization + tma_compute_bound_est + tma_irregular_overhead + tma_branching_overhead + tma_useful_work )",
"MetricExpr": "100 - ( tma_bottleneck_big_code + tma_bottleneck_instruction_fetch_bw + tma_bottleneck_mispredictions + tma_bottleneck_cache_memory_bandwidth + ma_bottleneck_cache_memory_latency + tma_bottleneck_memory_data_tlbs + tma_bottleneck_memory_synchronization + tma_bottleneck_compute_bound_est + tma_bottleneck_irregular_overhead + tma_bottleneck_branching_overhead + tma_bottleneck_useful_work )",
"MetricGroup": "BvOB;Cor;Offcore;TopdownL1;tma_L1_group;Scaled_Slots",
"MetricName": "tma_bottleneck_other_bottlenecks",
"MetricThreshold": "tma_bottleneck_other_bottlenecks > 20",
Expand Down Expand Up @@ -1633,7 +1633,7 @@
},
{
"BriefDescription": "Branch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
"MetricExpr": "tma_mispredictions * tma_info_thread_slots / ( 4 ) / BR_MISP_RETIRED.ALL_BRANCHES / 100",
"MetricExpr": "tma_bottleneck_mispredictions * tma_info_thread_slots / ( 4 ) / BR_MISP_RETIRED.ALL_BRANCHES / 100",
"MetricGroup": "Bad;BrMispredicts;Core_Metric;tma_issueBM",
"MetricName": "tma_info_bad_spec_branch_misprediction_cost",
"PublicDescription": "Branch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear). Related metrics: tma_bottleneck_mispredictions, tma_branch_mispredicts, tma_mispredicts_resteers."
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6 changes: 3 additions & 3 deletions EMR/metrics/emeraldrapids_metrics.json
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6 changes: 3 additions & 3 deletions EMR/metrics/perf/emeraldrapids_metrics_perf.json
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Expand Up @@ -326,7 +326,7 @@
},
{
"BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks (when the front-end could not sustain operations delivery to the back-end)",
"MetricExpr": "100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( 1 - INST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.MS\\,cmask\\=0x1@ ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_ms ) ) ) ) - tma_big_code",
"MetricExpr": "100 * ( tma_frontend_bound - ( 1 - ( 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts ) ) * tma_fetch_latency * tma_mispredicts_resteers / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) - ( ( 1 - INST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.MS\\,cmask\\=0x1@ ) * ( tma_fetch_latency * ( tma_ms_switches + tma_branch_resteers * ( tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts ) / ( tma_mispredicts_resteers + tma_clears_resteers + tma_unknown_branches ) ) / ( tma_icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + tma_lcp + tma_dsb_switches ) + tma_fetch_bandwidth * tma_ms / ( tma_mite + tma_dsb + tma_ms ) ) ) ) - tma_bottleneck_big_code",
"MetricGroup": "BvFB;Fed;FetchBW;Frontend;TopdownL1;tma_L1_group;Default;Scaled_Slots",
"MetricName": "tma_bottleneck_instruction_fetch_bw",
"MetricThreshold": "tma_bottleneck_instruction_fetch_bw > 20",
Expand Down Expand Up @@ -395,7 +395,7 @@
},
{
"BriefDescription": "Total pipeline cost of remaining bottlenecks in the back-end",
"MetricExpr": "100 - ( tma_big_code + tma_instruction_fetch_bw + tma_mispredictions + tma_cache_memory_bandwidth + tma_cache_memory_latency + tma_memory_data_tlbs + tma_memory_synchronization + tma_compute_bound_est + tma_irregular_overhead + tma_branching_overhead + tma_useful_work )",
"MetricExpr": "100 - ( tma_bottleneck_big_code + tma_bottleneck_instruction_fetch_bw + tma_bottleneck_mispredictions + tma_bottleneck_cache_memory_bandwidth + ma_bottleneck_cache_memory_latency + tma_bottleneck_memory_data_tlbs + tma_bottleneck_memory_synchronization + tma_bottleneck_compute_bound_est + tma_bottleneck_irregular_overhead + tma_bottleneck_branching_overhead + tma_bottleneck_useful_work )",
"MetricGroup": "BvOB;Cor;Offcore;TopdownL1;tma_L1_group;Default;Scaled_Slots",
"MetricName": "tma_bottleneck_other_bottlenecks",
"MetricThreshold": "tma_bottleneck_other_bottlenecks > 20",
Expand Down Expand Up @@ -1828,7 +1828,7 @@
},
{
"BriefDescription": "Branch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
"MetricExpr": "tma_mispredictions * tma_info_thread_slots / ( 6 ) / BR_MISP_RETIRED.ALL_BRANCHES / 100",
"MetricExpr": "tma_bottleneck_mispredictions * tma_info_thread_slots / ( 6 ) / BR_MISP_RETIRED.ALL_BRANCHES / 100",
"MetricGroup": "Bad;BrMispredicts;Core_Metric;tma_issueBM",
"MetricName": "tma_info_bad_spec_branch_misprediction_cost",
"PublicDescription": "Branch Misprediction Cost: Cycles representing fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear). Related metrics: tma_bottleneck_mispredictions, tma_branch_mispredicts, tma_mispredicts_resteers."
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