mapfile: Add ARL-H

[edwarddavidbaker]

This commit adds ARL-H model ID 0xC5 (https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/x86/include/asm/intel-family.h) to mapfile.csv. Crestmont event content and updates were merged in #229 .

[edwarddavidbaker]

• Currently updating scripts to support ARL.

[edwarddavidbaker]

@captain5050, @weilinwa, @kliang2

Currently I've updated mapfile.csv for ARL-H with the following rows. I believe this accurately reflects CPUID data.

• mapfile.csv columns Core Type and Core Role corresponds to Bits 31-24 Core Type.
• mapfile.csv column Native Model ID maps to Bits 23-00: Native model ID of the core.

Family-model	Version	Filename	EventType	Core Type	Native Model ID	Core Role Name
GenuineIntel-6-C5	V1.03	/ARL/events/arrowlake_skymont_core.json	hybridcore	0x20	0x000003	Atom
GenuineIntel-6-C5	V1.03	/ARL/events/arrowlake_crestmont_core.json	hybridcore	0x20	0x000002	Atom
GenuineIntel-6-C5	V1.03	/ARL/events/arrowlake_lioncove_core.json	hybridcore	0x40	0x000003	Core
GenuineIntel-6-C5	V1.03	/ARL/events/arrowlake_uncore.json	uncore

---

What do you think would be easiest for your workflows?

1. Continue with the above settings. Native Model ID creates unique rows.
2. Slightly deviate from CPUID/SDM and create a unique Core Role Name.

[edwarddavidbaker]

• I am restructuring this pull request to only focus on ARL to merge other platform updates.
• GNR, SRF, GRR, and MTL changes separated and submitted in GNR, SRF, GRR, MTL: Release event updates #221 .

[captain5050]

The converter script uses the 'Atom' value in the last column to select the PMU to program events on for hybrid systems. I think the crestmont one needs to be something like LowPower to differentiate from the skymont atom PMU:
https://lore.kernel.org/lkml/0525e13d-7439-4b42-af69-85aa33f5d3c8@linux.intel.com/
https://github.com/intel/perfmon/blob/main/scripts/create_perf_json.py#L1891

[edwarddavidbaker]

Thanks Ian. I updated the Crestmont mapfile.csv entry to use LowPower_Atom.

[edwarddavidbaker]

@captain5050 I added a few modifications to create_perf_json.py to support LowPower_Atom entries in mapfile.csv. A small dictionary helps connect mapfile entries to Linux cpu_core, cpu_atom, or cpu_lowpower.

<snip>
                if event_type == 'hybridcore':
                    # We want a core and an atom file, so change
                    # event_type for hybrid models. Mapfile.csv core
                    # roles are Core, Atom, or LowPower_Atom.
                    core_role_mapfile_to_linux_mapping = {
                        'Core': 'core',
                        'Atom': 'atom',
                        'LowPower_Atom': 'lowpower',
                    }
                    if core_role_name not in core_role_mapfile_to_linux_mapping:
                        raise ValueError(f'Unexpected core role {core_role_name}')
                    event_type = core_role_mapfile_to_linux_mapping[core_role_name]
<snip>

With these changes I compared the output from main and this feature branch.

diff -rup main/arrowlake/cache.json lowpower_atom/arrowlake/cache.json
--- main/arrowlake/cache.json   2024-09-26 12:40:07.961386838 -0700
+++ lowpower_atom/arrowlake/cache.json  2024-09-26 12:49:31.796885280 -0700
@@ -88,6 +88,16 @@
         "Unit": "cpu_core"
     },
     {
+        "BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.",
+        "Counter": "0,1,2,3,4,5,6,7",
+        "EventCode": "0x2e",
+        "EventName": "LONGEST_LAT_CACHE.REFERENCE",
+        "PublicDescription": "Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the core has access to an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",
+        "SampleAfterValue": "200003",
+        "UMask": "0x4f",
+        "Unit": "cpu_lowpower"
+    },
+    {
         "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss.",
         "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x35",
@@ -107,6 +117,16 @@
         "Unit": "cpu_atom"
     },
     {
+        "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache.",
+        "Counter": "0,1,2,3,4,5,6,7",
+        "EventCode": "0x35",
+        "EventName": "MEM_BOUND_STALLS_IFETCH.L2_HIT",
+        "PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the L2 cache.",
+        "SampleAfterValue": "1000003",
+        "UMask": "0x1",
+        "Unit": "cpu_lowpower"
+    },
+    {
         "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which missed in the L2 cache.",
         "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x35",
@@ -144,6 +164,16 @@
         "Unit": "cpu_atom"
     },
     {
+        "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache.",
+        "Counter": "0,1,2,3,4,5,6,7",
+        "EventCode": "0x34",
+        "EventName": "MEM_BOUND_STALLS_LOAD.L2_HIT",
+        "PublicDescription": "Counts the number of cycles a core is stalled due to a demand load which hit in the L2 cache.",
+        "SampleAfterValue": "1000003",
+        "UMask": "0x1",
+        "Unit": "cpu_lowpower"
+    },
+    {
         "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which missed in the L2 cache.",
         "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0x34",
@@ -384,6 +414,15 @@
         "Unit": "cpu_atom"
     },
     {
+        "BriefDescription": "Counts the number of load ops retired that hit the L1 data cache.",
+        "Counter": "0,1,2,3,4,5,6,7",
+        "EventCode": "0xd1",
+        "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
+        "SampleAfterValue": "200003",
+        "UMask": "0x1",
+        "Unit": "cpu_lowpower"
+    },
+    {
         "BriefDescription": "Counts the number of load ops retired that miss in the L1 data cache",
         "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xd1",
@@ -393,6 +432,15 @@
         "Unit": "cpu_atom"
     },
     {
+        "BriefDescription": "Counts the number of load ops retired that miss in the L1 data cache.",
+        "Counter": "0,1,2,3,4,5,6,7",
+        "EventCode": "0xd1",
+        "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
+        "SampleAfterValue": "200003",
+        "UMask": "0x40",
+        "Unit": "cpu_lowpower"
+    },
+    {
         "BriefDescription": "Counts the number of load ops retired that hit in the L2 cache",
         "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xd1",
@@ -403,6 +451,15 @@
         "Unit": "cpu_atom"
     },
     {
+        "BriefDescription": "Counts the number of load ops retired that hit in the L2 cache.",
+        "Counter": "0,1,2,3,4,5,6,7",
+        "EventCode": "0xd1",
+        "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
+        "SampleAfterValue": "200003",
+        "UMask": "0x2",
+        "Unit": "cpu_lowpower"
+    },
+    {
         "BriefDescription": "Counts the number of load ops retired that hit in the L3 cache.",
         "Counter": "0,1,2,3,4,5,6,7",
         "EventCode": "0xd1",

<snip>

diff -rup main/mapfile.csv lowpower_atom/mapfile.csv
--- main/mapfile.csv    2024-09-26 12:40:07.271376808 -0700
+++ lowpower_atom/mapfile.csv   2024-09-26 12:49:31.136880465 -0700
@@ -1,6 +1,6 @@
 GenuineIntel-6-(97|9A|B7|BA|BF),v1.27,alderlake,core
 GenuineIntel-6-BE,v1.27,alderlaken,core
-GenuineIntel-6-C6,v1.03,arrowlake,core
+GenuineIntel-6-C[56],v1.03,arrowlake,core
 GenuineIntel-6-(1C|26|27|35|36),v5,bonnell,core
 GenuineIntel-6-(3D|47),v30,broadwell,core
 GenuineIntel-6-56,v12,broadwellde,core

[edwarddavidbaker]

Thanks Ian.