Add power functionality

[mkorbel1]

Motivation

In SystemVerilog, power (a**b) is a useful function.

It would be nice to have a synthesizable Module and associated functions for generating hardware and SystemVerilog with powers.

Desired solution

• Create a new Module that generates a**b in output SystemVerilog and appropriately simulates powers in the ROHD simulator.
• Add functions (probably to Logic) to automatically generate this module in a convenient API.

Alternatives considered

No response

Additional details

No response