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Sort ports in generated outputs #395

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mkorbel1 opened this issue Jul 25, 2023 · 0 comments · Fixed by #420
Closed

Sort ports in generated outputs #395

mkorbel1 opened this issue Jul 25, 2023 · 0 comments · Fixed by #420
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enhancement New feature or request

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@mkorbel1
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Motivation

Currently the order of ports in generated SystemVerilog is somewhat random, which can make integration of the generated code a little annoying. It would be nice if the ports were organized.

Desired solution

It might be reasonable to sort them by name alphabetically, perhaps grouped only by name or maybe keeping inputs above outputs. Usually related ports might have the same prefix.

Alternatives considered

No response

Additional details

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@mkorbel1 mkorbel1 added the enhancement New feature or request label Jul 25, 2023
mkorbel1 added a commit to mkorbel1/rohd that referenced this issue Oct 4, 2023
@mkorbel1
Sort ports and internal signals, fix intel#395
5bba56b
@mkorbel1 mkorbel1 mentioned this issue Oct 4, 2023
Merged
mkorbel1 added a commit that referenced this issue Oct 9, 2023
@mkorbel1
Sort ports and internal signals, fix #395 (#420)
273d083
@mkorbel1 mkorbel1 mentioned this issue Nov 17, 2023
Merged
@mkorbel1 mkorbel1 self-assigned this Nov 17, 2023
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Sort ports and internal signals, fix #395 mkorbel1/rohd
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