Rk356x: Add NVMe and AHCI drivers.

jaredmcneill · Dec 23, 2021 · cbc85b1 · cbc85b1
1 parent 8d89a5a
commit cbc85b1
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Showing 6 changed files with 67 additions and 13 deletions.
diff --git a/edk2-rockchip/Platform/Pine64/Quartz64/AcpiTables/Dsdt.asl b/edk2-rockchip/Platform/Pine64/Quartz64/AcpiTables/Dsdt.asl
@@ -181,9 +181,16 @@ DefinitionBlock ("DsdtTable.aml", "DSDT",
           QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
             0x0000000000000000,   // Granularity
             0x0000000310000000,   // Range Minimum
-            0x000000033FFFFFFF,   // Range Maximum
+            0x000000033FFEFFFF,   // Range Maximum
             0x0000000000000000,   // Translation Offset
-            0x0000000030000000,   // Length
+            0x000000002FFF0000,   // Length
+          )
+          QWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+            0,                    // Granularity
+            0x0000,               // Range Minimum
+            0xFFFF,               // Range Maximum
+            0x000000033FFF0000,   // Translation Offset
+            0x10000,              // Length
           )
         })
         return (RBUF)

diff --git a/edk2-rockchip/Platform/Pine64/Quartz64/Quartz64.dsc b/edk2-rockchip/Platform/Pine64/Quartz64/Quartz64.dsc
@@ -174,6 +174,9 @@
   PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
   PciHostBridgeLib|Silicon/Rockchip/Rk356x/Library/Rk356xPciHostBridgeLib/Rk356xPciHostBridgeLib.inf
 
+  # Storage
+  UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
+
 [LibraryClasses.common.SEC]
   PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
   BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
@@ -434,7 +437,12 @@
   gArmTokenSpaceGuid.PcdPciMmio32Base|0xF4000000
   gArmTokenSpaceGuid.PcdPciMmio32Size|0x02000000
   gArmTokenSpaceGuid.PcdPciMmio64Base|0x0000000310000000
-  gArmTokenSpaceGuid.PcdPciMmio64Size|0x0000000030000000
+  gArmTokenSpaceGuid.PcdPciMmio64Size|0x000000002FFF0000
+  gArmTokenSpaceGuid.PcdPciIoBase|0x0000
+  gArmTokenSpaceGuid.PcdPciIoSize|0x10000
+  gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|34
+
+  gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation|0x000000033FFF0000
   gRk356xTokenSpaceGuid.PcdPcieResetGpioBank|1
   gRk356xTokenSpaceGuid.PcdPcieResetGpioPin|10
   gRk356xTokenSpaceGuid.PcdPciePowerGpioBank|0
@@ -518,7 +526,7 @@
   MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
 
   ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
-  UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
+  ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
   ArmPkg/Drivers/TimerDxe/TimerDxe.inf
   MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
   MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
@@ -585,6 +593,17 @@
   Silicon/Rockchip/Rk356x/Drivers/PciHostDxe/PciHostDxe.inf
   MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
   MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+  EmbeddedPkg/Drivers/NonCoherentIoMmuDxe/NonCoherentIoMmuDxe.inf
+  MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+
+  #
+  # AHCI Support
+  #
+  MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+  MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+  MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+  MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+  MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
 
   #
   # RAM Disk Support

diff --git a/edk2-rockchip/Platform/Rockchip/Rk356x/Rk356x.fdf b/edk2-rockchip/Platform/Rockchip/Rk356x/Rk356x.fdf
@@ -115,7 +115,7 @@ READ_LOCK_STATUS   = TRUE
   INF Silicon/Rockchip/Rk356x/Drivers/DisplayDxe/DisplayDxe.inf
   INF EmbeddedPkg/Drivers/ConsolePrefDxe/ConsolePrefDxe.inf
 
-  INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
+  INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
   INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
   INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
   INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
@@ -169,13 +169,24 @@ READ_LOCK_STATUS   = TRUE
   INF Silicon/Rockchip/Rk356x/Drivers/PciHostDxe/PciHostDxe.inf
   INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
   INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+  INF EmbeddedPkg/Drivers/NonCoherentIoMmuDxe/NonCoherentIoMmuDxe.inf
+  INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
 
   #
   # eMMC
   #
   #INF EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf
   #INF Silicon/Rockchip/Rk356x/Drivers/DwEmmcDxe/DwEmmcDxe.inf
 
+  #
+  # AHCI Support
+  #
+  INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+  INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+  INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+  INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+  INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+
   #
   # RAM Disk Support
   #

diff --git a/edk2-rockchip/Silicon/Rockchip/Rk356x/Drivers/PciHostDxe/PciHostDxe.c b/edk2-rockchip/Silicon/Rockchip/Rk356x/Drivers/PciHostDxe/PciHostDxe.c
@@ -54,6 +54,7 @@
 #define IATU_REGION_CTRL_INBOUND(n)     (ATU_CAP_BASE + ((n) << 9) + 0x100)
 #define IATU_REGION_CTRL_1_OFF          0x000
 #define  IATU_TYPE_MEM                  0
+#define  IATU_TYPE_IO                   2
 #define  IATU_TYPE_CFG0                 4
 #define  IATU_TYPE_CFG1                 5
 #define IATU_REGION_CTRL_2_OFF          0x004
@@ -280,6 +281,8 @@ InitializePciHost (
   UINT64                   Cfg0Size;
   UINT64                   Cfg1Base;
   UINT64                   Cfg1Size;
+  UINT64                   PciIoBase;
+  UINT64                   PciIoSize;
 
   /* Configure MULTI-PHY */
   CruSetPciePhySource (2, 0);
@@ -314,9 +317,13 @@ InitializePciHost (
   Cfg0Base = SIZE_1MB;
   Cfg0Size = SIZE_64KB;
   Cfg1Base = SIZE_2MB;
-  Cfg1Size = 0x10000000UL - SIZE_2MB;
+  Cfg1Size = 0x10000000UL - (SIZE_2MB + SIZE_64KB);
+  PciIoBase = 0x2FFF0000UL;
+  PciIoSize = SIZE_64KB;
+
   PciSetupAtu (DbiBase, 0, IATU_TYPE_CFG0, 0x300000000UL + Cfg0Base, Cfg0Base, Cfg0Size);
   PciSetupAtu (DbiBase, 1, IATU_TYPE_CFG1, 0x300000000UL + Cfg1Base, Cfg1Base, Cfg1Size);
+  PciSetupAtu (DbiBase, 2, IATU_TYPE_IO,   0x300000000UL + PciIoBase, 0, PciIoSize);
 
   DEBUG ((DEBUG_INFO, "PCIe: Start LTSSM\n"));
   PciEnableLtssm (ApbBase, FALSE);

diff --git a/edk2-rockchip/Silicon/Rockchip/Rk356x/Library/Rk356xPciHostBridgeLib/PciHostBridgeLib.c b/edk2-rockchip/Silicon/Rockchip/Rk356x/Library/Rk356xPciHostBridgeLib/PciHostBridgeLib.c
@@ -75,18 +75,27 @@ PciHostBridgeGetRootBridges (
 
   RootBridge->Segment     = 0;
 
-  RootBridge->Supports    = 0;
+  RootBridge->Supports    = EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO |
+                            EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO |
+                            EFI_PCI_ATTRIBUTE_ISA_IO_16 |
+                            EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO | \
+                            EFI_PCI_ATTRIBUTE_VGA_MEMORY | \
+                            EFI_PCI_ATTRIBUTE_VGA_IO_16  | \
+                            EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;
   RootBridge->Attributes  = RootBridge->Supports;
 
-  RootBridge->DmaAbove4G  = TRUE;
+  RootBridge->DmaAbove4G            = TRUE;
+  RootBridge->ResourceAssigned      = FALSE;
+  RootBridge->NoExtendedConfigSpace = FALSE;
 
   RootBridge->AllocationAttributes  = EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM |
-                                      EFI_PCI_HOST_BRIDGE_MEM64_DECODE ;
+                                      EFI_PCI_HOST_BRIDGE_MEM64_DECODE;
 
   RootBridge->Bus.Base              = PcdGet32 (PcdPciBusMin);
   RootBridge->Bus.Limit             = PcdGet32 (PcdPciBusMax);
-  RootBridge->Io.Base               = MAX_UINT64;
-  RootBridge->Io.Limit              = 0;
+  RootBridge->Io.Base               = PcdGet64 (PcdPciIoBase);
+  RootBridge->Io.Limit              = PcdGet64 (PcdPciIoBase) + PcdGet64 (PcdPciIoSize) - 1;
+  RootBridge->Io.Translation        = MAX_UINT64 - PcdGet64 (PcdPciIoTranslation) + 1;
   RootBridge->Mem.Base              = PcdGet32 (PcdPciMmio32Base);
   RootBridge->Mem.Limit             = PcdGet32 (PcdPciMmio32Base) + PcdGet32 (PcdPciMmio32Size) - 1;
   RootBridge->MemAbove4G.Base       = PcdGet64 (PcdPciMmio64Base);
@@ -103,8 +112,6 @@ PciHostBridgeGetRootBridges (
   ASSERT (FixedPcdGet64 (PcdPciMmio32Translation) == 0);
   ASSERT (FixedPcdGet64 (PcdPciMmio64Translation) == 0);
 
-  RootBridge->NoExtendedConfigSpace = FALSE;
-
   RootBridge->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath;
 
   return RootBridge;

diff --git a/...ockchip/Silicon/Rockchip/Rk356x/Library/Rk356xPciHostBridgeLib/Rk356xPciHostBridgeLib.inf b/...ockchip/Silicon/Rockchip/Rk356x/Library/Rk356xPciHostBridgeLib/Rk356xPciHostBridgeLib.inf
@@ -39,6 +39,9 @@
 [FixedPcd]
   gArmTokenSpaceGuid.PcdPciBusMin
   gArmTokenSpaceGuid.PcdPciBusMax
+  gArmTokenSpaceGuid.PcdPciIoBase
+  gArmTokenSpaceGuid.PcdPciIoSize
+  gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation
   gArmTokenSpaceGuid.PcdPciMmio32Base
   gArmTokenSpaceGuid.PcdPciMmio32Size
   gEfiMdePkgTokenSpaceGuid.PcdPciMmio32Translation