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[WIP][MooreToCore] Fix conversion to vector of bit
$ ./bin/circt-verilog /tmp/string_bit_array.sv module { hw.module @top() { %0 = llhd.constant_time <0ns, 0d, 1e> %c0_i80 = hw.constant 0 : i80 %c6_i4 = hw.constant 6 : i4 %c0_i112 = hw.constant 0 : i112 %a = llhd.sig %c0_i112 : i112 llhd.process { %1 = builtin.unrealized_conversion_cast %c6_i4 : i4 to i32 %2 = comb.concat %c0_i80, %1 : i80, i32 llhd.drv %a, %2 after %0 : !hw.inout<i112> llhd.halt } hw.output } }
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