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🚧 POC - support NaNs for SSE & AVX2 f32 #18

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🚧 POC - support NaNs for SSE & AVX2 f32 #18

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6ffb4db
:construction: partially supported NaNs for SSE f32
jvdd Feb 4, 2023
188635f
:broom: cleanup code + return NaN index twice if only identified as e…
jvdd Feb 5, 2023
7ac2504
:broom: formatting
jvdd Feb 5, 2023
bf1725b
:mag: enable lto
jvdd Feb 6, 2023
0a66127
:thinking: implement avx2 as well
jvdd Feb 6, 2023
08588bb
:see_no_evil: check for avx2 instead of avx
jvdd Feb 6, 2023
2bd0f8e
:bug: check for avx2 instead of avx in benches
jvdd Feb 6, 2023
faa3f56
:see_no_evil: remove avx from runtime feature detection checks
jvdd Feb 6, 2023
50ee420
:see_no_evil:
jvdd Feb 6, 2023
4f9b767
:pen: undo rename so that codspeed can compare
jvdd Feb 6, 2023
bae6139
:bug: load unaligned
jvdd Feb 7, 2023
df40466
:zap: use faster SIMD intrinsics
jvdd Feb 7, 2023
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3 changes: 3 additions & 0 deletions Cargo.toml
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Original file line number Diff line number Diff line change
Expand Up @@ -26,6 +26,9 @@ codspeed-criterion-compat = "1.0.1"
criterion = "0.3.1"
dev_utils = { path = "dev_utils" }

[profile.release]
lto = true


[[bench]]
name = "bench_f16"
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8 changes: 4 additions & 4 deletions benches/bench_f32.rs
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Expand Up @@ -26,7 +26,7 @@ fn minmax_f32_random_array_long(c: &mut Criterion) {
});
}
#[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
if is_x86_feature_detected!("avx") {
if is_x86_feature_detected!("avx2") {
c.bench_function("avx_random_long_f32", |b| {
b.iter(|| unsafe { AVX2::argminmax(black_box(data)) })
});
Expand Down Expand Up @@ -67,7 +67,7 @@ fn minmax_f32_random_array_short(c: &mut Criterion) {
});
}
#[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
if is_x86_feature_detected!("avx") {
if is_x86_feature_detected!("avx2") {
c.bench_function("avx_random_short_f32", |b| {
b.iter(|| unsafe { AVX2::argminmax(black_box(data)) })
});
Expand Down Expand Up @@ -108,7 +108,7 @@ fn minmax_f32_worst_case_array_long(c: &mut Criterion) {
});
}
#[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
if is_x86_feature_detected!("avx") {
if is_x86_feature_detected!("avx2") {
c.bench_function("avx_worst_long_f32", |b| {
b.iter(|| unsafe { AVX2::argminmax(black_box(data)) })
});
Expand Down Expand Up @@ -149,7 +149,7 @@ fn minmax_f32_worst_case_array_short(c: &mut Criterion) {
});
}
#[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
if is_x86_feature_detected!("avx") {
if is_x86_feature_detected!("avx2") {
c.bench_function("avx_worst_short_f32", |b| {
b.iter(|| unsafe { AVX2::argminmax(black_box(data)) })
});
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5 changes: 3 additions & 2 deletions src/lib.rs
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Expand Up @@ -125,10 +125,11 @@ macro_rules! impl_argminmax {
return unsafe { AVX512::argminmax(self) }
} else if is_x86_feature_detected!("avx2") {
return unsafe { AVX2::argminmax(self) }
} else if is_x86_feature_detected!("avx") & (<$t>::NB_BITS >= 32) & (<$t>::IS_FLOAT == true) {
// TODO: current NaN handling requires avx2
} else if is_x86_feature_detected!("avx") & (<$t>::NB_BITS >= 64) & (<$t>::IS_FLOAT == true) {
// f32 and f64 do not require avx2
return unsafe { AVX2::argminmax(self) }
// SKIP SSE4.2 bc scalar is faster or equivalent for 64 bit numbers
// // SKIP SSE4.2 bc scalar is faster or equivalent for 64 bit numbers
// // } else if is_x86_feature_detected!("sse4.2") & (<$t>::NB_BITS == 64) & (<$t>::IS_FLOAT == false) {
// // SSE4.2 is needed for comparing 64-bit integers
// return unsafe { SSE::argminmax(self) }
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10 changes: 9 additions & 1 deletion src/scalar/generic.rs
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Expand Up @@ -22,7 +22,15 @@ pub fn scalar_argminmax<T: Copy + PartialOrd>(arr: &[T]) -> (usize, usize) {
let mut high: T = unsafe { *arr.get_unchecked(high_index) };
for i in 0..arr.len() {
let v: T = unsafe { *arr.get_unchecked(i) };
if v < low {
if v != v {
// TODO: optimize this
// Handle NaNs: if value is NaN, than return index of that value
return (i, i);
// low = v;
// low_index = i;
// high = v;
// high_index = i;
} else if v < low {
low = v;
low_index = i;
} else if v > high {
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8 changes: 4 additions & 4 deletions src/simd/generic.rs
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Expand Up @@ -122,11 +122,11 @@ pub trait SIMD<
// Self::_mm_prefetch(arr.as_ptr().add(start));
let (min_index_, min_value_, max_index_, max_value_) =
Self::_core_argminmax(&arr[start..start + dtype_max]);
if min_value_ < min_value {
if min_value_ < min_value || min_value_ != min_value_ {
min_index = start + min_index_;
min_value = min_value_;
}
if max_value_ > max_value {
if max_value_ > max_value || max_value_ != max_value_ {
max_index = start + max_index_;
max_value = max_value_;
}
Expand All @@ -137,11 +137,11 @@ pub trait SIMD<
// Self::_mm_prefetch(arr.as_ptr().add(start));
let (min_index_, min_value_, max_index_, max_value_) =
Self::_core_argminmax(&arr[start..]);
if min_value_ < min_value {
if min_value_ < min_value || min_value_ != min_value_ {
min_index = start + min_index_;
min_value = min_value_;
}
if max_value_ > max_value {
if max_value_ > max_value || max_value_ != max_value_ {
max_index = start + max_index_;
max_value = max_value_;
}
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