ARM-Processor

A pipelined implementation of ARM processor

Processor Specifications

This CPU has a 32-bit data bus and a 32-bit address bus.

All of the instructions are 32-bit.

Instructions:

Instruction Mnemonic	Definition	Bits 27:26	Bits 24:21
MOV	Move	00	1101
MVN	Move NOT	00	1111
ADD	Add	00	0100
ADC	Add with Carry	00	0101
SUB	Subtract	00	0010
SBC	Subtract with Carry	00	0110
AND	Logical AND	00	0000
ORR	Logical OR	00	1100
EOR	Exclusive OR	00	0001
CMP	Compare	00	1010
TST	Test	00	1000
LDR	Load Register	01	0100
STR	Store Register	01	0100
B	Branch	10	XXXX

Name		Name	Last commit message	Last commit date
Latest commit History 14 Commits
ALU.v		ALU.v
ARM.v		ARM.v
ARM_TB.v		ARM_TB.v
Adder.v		Adder.v
Condition_Check.v		Condition_Check.v
Control_Unit.v		Control_Unit.v
EXE_Reg.v		EXE_Reg.v
EXE_Stage.v		EXE_Stage.v
Forwarding_Unit.v		Forwarding_Unit.v
Hazard_Detection_Unit.v		Hazard_Detection_Unit.v
ID_Reg.v		ID_Reg.v
ID_Stage.v		ID_Stage.v
IF_Reg.v		IF_Reg.v
IF_Stage.v		IF_Stage.v
Instruction_Mem.v		Instruction_Mem.v
MEM_Reg.v		MEM_Reg.v
MEM_Stage.v		MEM_Stage.v
MUX_2_to_1.v		MUX_2_to_1.v
MUX_4_to_1.v		MUX_4_to_1.v
Memory.v		Memory.v
PC.v		PC.v
README.md		README.md
Register_File.v		Register_File.v
Status_Reg.v		Status_Reg.v
WB_Stage.v		WB_Stage.v
settings.h		settings.h
val2_generator.v		val2_generator.v