Merge pull request rust-lang#32 from alexcrichton/tests2

Migrate existing tests to #[assert_instr]
kazcw · Sep 20, 2017 · a5e7383 · a5e7383
2 parents 55677c8 + 97f9eea
commit a5e7383
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diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md
@@ -14,6 +14,7 @@ example for `_mm_adds_epi16`:
 /// Add packed 16-bit integers in `a` and `b` using saturation.
 #[inline(always)]
 #[target_feature = "+sse2"]
+#[cfg_attr(test, assert_instr(paddsw))]
 pub fn _mm_adds_epi16(a: i16x8, b: i16x8) -> i16x8 {
     unsafe { paddsw(a, b) }
 }
@@ -32,6 +33,10 @@ Let's break this down:
   support `sse2`, the compiler will still generate code for `_mm_adds_epi16`
   *as if* `sse2` support existed. Without this attribute, the compiler might
   not generate the intended CPU instruction.
+* The `#[cfg_attr(test, assert_instr(paddsw))]` attribute indicates that when
+  we're testing the crate we'll assert that the `paddsw` instruction is
+  generated inside this function, ensuring that the SIMD intrinsic truly is an
+  intrinsic for the instruction!
 * The types of the vectors given to the intrinsic should generally match the
   types as provided in the vendor interface. We'll talk about this more below.
 * The implementation of the vendor intrinsic is generally very simple.
@@ -40,7 +45,7 @@ Let's break this down:
   compiler intrinsic (in this case, `paddsw`) when one is available. More on
   this below as well.
 
-Once a function has been added, you should add at least one test for basic
+Once a function has been added, you should also add at least one test for basic
 functionality. Here's an example for `_mm_adds_epi16`:
 
 ```rust

diff --git a/asm/x86_bmi2_bzhi.asm b/asm/x86_bmi2_bzhi.asm
diff --git a/asm/x86_bmi2_bzhi.rs b/asm/x86_bmi2_bzhi.rs
diff --git a/asm/x86_bmi2_mulx.asm b/asm/x86_bmi2_mulx.asm
diff --git a/asm/x86_bmi2_mulx.rs b/asm/x86_bmi2_mulx.rs
diff --git a/asm/x86_bmi2_pdep.asm b/asm/x86_bmi2_pdep.asm
diff --git a/asm/x86_bmi2_pdep.rs b/asm/x86_bmi2_pdep.rs
diff --git a/asm/x86_bmi2_pext.asm b/asm/x86_bmi2_pext.asm
diff --git a/asm/x86_bmi2_pext.rs b/asm/x86_bmi2_pext.rs
diff --git a/asm/x86_bmi_andn.asm b/asm/x86_bmi_andn.asm
diff --git a/asm/x86_bmi_andn.rs b/asm/x86_bmi_andn.rs
diff --git a/asm/x86_bmi_bextr.asm b/asm/x86_bmi_bextr.asm
diff --git a/asm/x86_bmi_bextr.rs b/asm/x86_bmi_bextr.rs
diff --git a/asm/x86_bmi_blsi.asm b/asm/x86_bmi_blsi.asm
diff --git a/asm/x86_bmi_blsi.rs b/asm/x86_bmi_blsi.rs
diff --git a/asm/x86_bmi_blsr.asm b/asm/x86_bmi_blsr.asm
diff --git a/asm/x86_bmi_blsr.rs b/asm/x86_bmi_blsr.rs
diff --git a/asm/x86_bmi_tzcnt.asm b/asm/x86_bmi_tzcnt.asm
diff --git a/asm/x86_bmi_tzcnt.rs b/asm/x86_bmi_tzcnt.rs
diff --git a/asm/x86_lzcnt_lzcnt.asm b/asm/x86_lzcnt_lzcnt.asm
diff --git a/asm/x86_lzcnt_lzcnt.rs b/asm/x86_lzcnt_lzcnt.rs
diff --git a/asm/x86_popcnt_popcnt.asm b/asm/x86_popcnt_popcnt.asm
diff --git a/asm/x86_popcnt_popcnt.rs b/asm/x86_popcnt_popcnt.rs
diff --git a/asm/x86_tbm_blcfill.asm b/asm/x86_tbm_blcfill.asm
diff --git a/asm/x86_tbm_blcfill.rs b/asm/x86_tbm_blcfill.rs
diff --git a/asm/x86_tbm_blci.asm b/asm/x86_tbm_blci.asm
diff --git a/asm/x86_tbm_blci.rs b/asm/x86_tbm_blci.rs