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1. LC3-Verification LC3-Verification Public

   Verification of a 5 stage LC3 pipelined CPU with System Verilog and Mentor Graphics ModelSim

   SystemVerilog 8

2. Tridiagonal-Matrix-Inversion Tridiagonal-Matrix-Inversion Public

   Verilog design of the 10x10 Tridiagonal Matrix Inversion hardware accelerator using synopsys design compiler.

   Verilog 2 3

3. Cache Cache Public

   Cache Hierarchy simulator

   C++

4. 2D_Convolution 2D_Convolution Public

   CUDA optimization of 2D Convolution

   Cuda

5. UVM_Decode UVM_Decode Public

   Verification of Decode Stage using UVM

   SystemVerilog