This work presents an optimized algorithm for synthesizing arbitrary digital logic functions for MEM relay based circuits. The work leverages multiple matrix reduction optimizations and outputs structural verilog. The algorithm is implemented in Matlab and can be found in the "source_code" directory. The top level file is "main.m."
To View Abstract, Visit: https://krdwan.github.io/thesis
To View Full Thesis, Visit: http://icslwebs.ee.ucla.edu/dejan/researchwiki/images/b/bf/Kevin_Dwan_MS_Thesis.pdf