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[arch][riscv][nuclei] Add Nuclei RISC-V processsor support #281
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[arch][riscv][nuclei] Add Nuclei RISC-V processsor support #281
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* This PR add Nuclei RISC-V Processor which use CLIC interrupt system instead of PLIC and CLINT interrupt system * This PR is also using Nuclei NMSIS and SDK, see https://github.com/Nuclei-Software/NMSIS and https://github.com/Nuclei-Software/nuclei-sdk * In this PR, the context switch is done using CLIC software interrupt * For RISC-V CLIC spec, please check https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc * To evaluate this support, Nuclei HummingBird RISC-V SoC is supported, please check https://nucleisys.com/developboard.php for this board introduction Signed-off-by: Huaqi Fang <578567190@qq.com>
How to use this PRHere are steps used in Linux, similar steps could be done in Windows. Prerequisites
Assume you have extracted Nuclei Studio IDE into export PATH=$HOME/NucleiStudio_IDE_202009/NucleiStudio/toolchain/gcc/bin:$PATH Build Project for Nuclei HummingBird Evaluation Board
Thanks |
Oh very neat! Very interesting. The context switch thing we might have to work out a bit, but I'm always interested in new hardware. |
Signed-off-by: Huaqi Fang <578567190@qq.com>
Signed-off-by: Huaqi Fang <578567190@qq.com>
Signed-off-by: Huaqi Fang <578567190@qq.com>
Still looking at this one. Trouble is that context switch stuff is far too intrusive. Is it mandatory that the context switch be done via the CLIC? I'd love for this to look much more like the other riscv with the core kernel stuff. |
Yes, it should be done via CLIC, since CLIC introduced, CORE will have exception and interrupt state, if we use current context switch, then we can't get out of interrupt state, which will affect normal interrupt handling. |
Add Nuclei RISC-V Processor Support
https://github.com/Nuclei-Software/nuclei-sdk