Skip to content

Commit

Permalink
remove 'std_' before ieee754 operations
Browse files Browse the repository at this point in the history
  • Loading branch information
@jiahanxie353
jiahanxie353 committed Nov 15, 2024
1 parent b4ba003 commit 2df5e9d
Show file tree
Hide file tree
Showing 3 changed files with 13 additions and 13 deletions.
20 changes: 10 additions & 10 deletions include/circt/Dialect/Calyx/CalyxPrimitives.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -257,8 +257,8 @@ def SeqMemoryOp : CalyxPrimitive<"seq_mem", []> {
}];
}

class CalyxLibraryOp<string mnemonic, list<Trait> traits = []> :
CalyxPrimitive<"std_" # mnemonic, traits> {
class CalyxLibraryOp<string mnemonic, string prefix = "std_", list<Trait> traits = []> :
CalyxPrimitive<prefix # mnemonic, traits> {

let summary = "Defines an operation which maps to a Calyx library primitive";
let description = [{
Expand Down Expand Up @@ -289,7 +289,7 @@ class CalyxLibraryOp<string mnemonic, list<Trait> traits = []> :
];
}

class BoolBinaryLibraryOp<string mnemonic> : CalyxLibraryOp<mnemonic, [
class BoolBinaryLibraryOp<string mnemonic> : CalyxLibraryOp<mnemonic, "std_", [
Combinational,
SameTypeConstraint<"left", "right">
]> {
Expand All @@ -309,13 +309,13 @@ def SneqLibOp : BoolBinaryLibraryOp<"sneq"> {}
def SgeLibOp : BoolBinaryLibraryOp<"sge"> {}
def SleLibOp : BoolBinaryLibraryOp<"sle"> {}

class ArithBinaryLibraryOp<string mnemonic, list<Trait> traits = []> :
CalyxLibraryOp<mnemonic, !listconcat(traits, [
class ArithBinaryLibraryOp<string mnemonic, string prefix, list<Trait> traits = []> :
CalyxLibraryOp<mnemonic, prefix, !listconcat(traits, [
SameTypeConstraint<"left", "right">
])> {}

class CombinationalArithBinaryLibraryOp<string mnemonic> :
ArithBinaryLibraryOp<mnemonic, [
ArithBinaryLibraryOp<mnemonic, "std_", [
Combinational,
SameTypeConstraint<"left", "out">
]> {
Expand All @@ -332,7 +332,7 @@ def AndLibOp : CombinationalArithBinaryLibraryOp<"and"> {}
def OrLibOp : CombinationalArithBinaryLibraryOp<"or"> {}
def XorLibOp : CombinationalArithBinaryLibraryOp<"xor"> {}

class ArithBinaryFloatingPointLibraryOp<string mnemonic> : ArithBinaryLibraryOp<mnemonic, [
class ArithBinaryFloatingPointLibraryOp<string mnemonic> : ArithBinaryLibraryOp<mnemonic, "", [
SameTypeConstraint<"left", "out">]> {}

def AddFNOp : ArithBinaryFloatingPointLibraryOp<"ieee754.add"> {
Expand Down Expand Up @@ -410,7 +410,7 @@ def MulFNOp : ArithBinaryFloatingPointLibraryOp<"ieee754.mul"> {
}];
}

def MuxLibOp : CalyxLibraryOp<"mux", [
def MuxLibOp : CalyxLibraryOp<"mux", "std_", [
Combinational, SameTypeConstraint<"tru", "fal">, SameTypeConstraint<"tru", "out">
]> {
let results = (outs I1:$cond, AnyType:$tru, AnyType:$fal, AnyType:$out);
Expand All @@ -432,7 +432,7 @@ def MuxLibOp : CalyxLibraryOp<"mux", [
}];
}

class ArithBinaryPipeLibraryOp<string mnemonic> : ArithBinaryLibraryOp<mnemonic # "_pipe", [
class ArithBinaryPipeLibraryOp<string mnemonic> : ArithBinaryLibraryOp<mnemonic # "_pipe", "std_", [
SameTypeConstraint<"left", "out">
]> {
let results = (outs I1:$clk, I1:$reset, I1:$go, AnyType:$left, AnyType:$right, AnyType:$out, I1:$done);
Expand All @@ -445,7 +445,7 @@ def RemUPipeLibOp : ArithBinaryPipeLibraryOp<"remu"> {}
def RemSPipeLibOp : ArithBinaryPipeLibraryOp<"rems"> {}

class UnaryLibraryOp<string mnemonic, list<Trait> traits = []> :
CalyxLibraryOp<mnemonic, !listconcat(traits, [Combinational])> {
CalyxLibraryOp<mnemonic, "std_", !listconcat(traits, [Combinational])> {
let results = (outs AnyInteger:$in, AnyInteger:$out);
}

Expand Down
2 changes: 1 addition & 1 deletion test/Conversion/SCFToCalyx/convert_simple.mlir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -265,7 +265,7 @@ module {
// CHECK: %cst = calyx.constant @cst_0 <4.200000e+00 : f32> : i32
// CHECK-DAG: %true = hw.constant true
// CHECK-DAG: %mulf_0_reg.in, %mulf_0_reg.write_en, %mulf_0_reg.clk, %mulf_0_reg.reset, %mulf_0_reg.out, %mulf_0_reg.done = calyx.register @mulf_0_reg : i32, i1, i1, i1, i32, i1
// CHECK-DAG: %std_mulFN_0.clk, %std_mulFN_0.reset, %std_mulFN_0.go, %std_mulFN_0.control, %std_mulFN_0.left, %std_mulFN_0.right, %std_mulFN_0.roundingMode, %std_mulFN_0.out, %std_mulFN_0.exceptionalFlags, %std_mulFN_0.done = calyx.std_ieee754.mul @std_mulFN_0 : i1, i1, i1, i1, i32, i32, i3, i32, i5, i1
// CHECK-DAG: %std_mulFN_0.clk, %std_mulFN_0.reset, %std_mulFN_0.go, %std_mulFN_0.control, %std_mulFN_0.left, %std_mulFN_0.right, %std_mulFN_0.roundingMode, %std_mulFN_0.out, %std_mulFN_0.exceptionalFlags, %std_mulFN_0.done = calyx.ieee754.mul @std_mulFN_0 : i1, i1, i1, i1, i32, i32, i3, i32, i5, i1
// CHECK-DAG: %ret_arg0_reg.in, %ret_arg0_reg.write_en, %ret_arg0_reg.clk, %ret_arg0_reg.reset, %ret_arg0_reg.out, %ret_arg0_reg.done = calyx.register @ret_arg0_reg : i32, i1, i1, i1, i32, i1
// CHECK: calyx.group @bb0_0 {
// CHECK-DAG: calyx.assign %std_mulFN_0.left = %in0 : i32
Expand Down
4 changes: 2 additions & 2 deletions test/Dialect/Calyx/emit.mlir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -291,7 +291,7 @@ module attributes {calyx.entrypoint = "main"} {
%true = hw.constant true
%false = hw.constant false
%addf_0_reg.in, %addf_0_reg.write_en, %addf_0_reg.clk, %addf_0_reg.reset, %addf_0_reg.out, %addf_0_reg.done = calyx.register @addf_0_reg : i32, i1, i1, i1, i32, i1
%std_addFN_0.clk, %std_addFN_0.reset, %std_addFN_0.go, %std_addFN_0.control, %std_addFN_0.subOp, %std_addFN_0.left, %std_addFN_0.right, %std_addFN_0.roundingMode, %std_addFN_0.out, %std_addFN_0.exceptionalFlags, %std_addFN_0.done = calyx.std_ieee754.add @std_addFN_0 : i1, i1, i1, i1, i1, i32, i32, i3, i32, i5, i1
%std_addFN_0.clk, %std_addFN_0.reset, %std_addFN_0.go, %std_addFN_0.control, %std_addFN_0.subOp, %std_addFN_0.left, %std_addFN_0.right, %std_addFN_0.roundingMode, %std_addFN_0.out, %std_addFN_0.exceptionalFlags, %std_addFN_0.done = calyx.ieee754.add @std_addFN_0 : i1, i1, i1, i1, i1, i32, i32, i3, i32, i5, i1
%ret_arg0_reg.in, %ret_arg0_reg.write_en, %ret_arg0_reg.clk, %ret_arg0_reg.reset, %ret_arg0_reg.out, %ret_arg0_reg.done = calyx.register @ret_arg0_reg : i32, i1, i1, i1, i32, i1
calyx.wires {
calyx.assign %out0 = %ret_arg0_reg.out : i32
Expand Down Expand Up @@ -342,7 +342,7 @@ module attributes {calyx.entrypoint = "main"} {
%cst = calyx.constant @cst_0 <4.200000e+00 : f32> : i32
%true = hw.constant true
%mulf_0_reg.in, %mulf_0_reg.write_en, %mulf_0_reg.clk, %mulf_0_reg.reset, %mulf_0_reg.out, %mulf_0_reg.done = calyx.register @mulf_0_reg : i32, i1, i1, i1, i32, i1
%std_mulFN_0.clk, %std_mulFN_0.reset, %std_mulFN_0.go, %std_mulFN_0.control, %std_mulFN_0.left, %std_mulFN_0.right, %std_mulFN_0.roundingMode, %std_mulFN_0.out, %std_mulFN_0.exceptionalFlags, %std_mulFN_0.done = calyx.std_ieee754.mul @std_mulFN_0 : i1, i1, i1, i1, i32, i32, i3, i32, i5, i1
%std_mulFN_0.clk, %std_mulFN_0.reset, %std_mulFN_0.go, %std_mulFN_0.control, %std_mulFN_0.left, %std_mulFN_0.right, %std_mulFN_0.roundingMode, %std_mulFN_0.out, %std_mulFN_0.exceptionalFlags, %std_mulFN_0.done = calyx.ieee754.mul @std_mulFN_0 : i1, i1, i1, i1, i32, i32, i3, i32, i5, i1
%ret_arg0_reg.in, %ret_arg0_reg.write_en, %ret_arg0_reg.clk, %ret_arg0_reg.reset, %ret_arg0_reg.out, %ret_arg0_reg.done = calyx.register @ret_arg0_reg : i32, i1, i1, i1, i32, i1
calyx.wires {
calyx.assign %out0 = %ret_arg0_reg.out : i32
Expand Down

0 comments on commit 2df5e9d

Please sign in to comment.