[DC] Add merge lowering

lib/Conversion/DCToHW/DCToHW.cpp

@@ -656,6 +656,46 @@ class BranchConversionPattern : public OpConversionPattern<BranchOp> {
   }
 };
 
+class MergeConversionPattern : public OpConversionPattern<MergeOp> {
+public:
+  using OpConversionPattern::OpConversionPattern;
+  LogicalResult
+  matchAndRewrite(MergeOp op, OpAdaptor operands,
+                  ConversionPatternRewriter &rewriter) const override {
+    auto bb = BackedgeBuilder(rewriter, op.getLoc());
+    UnwrappedIO io = unwrapIO(op, operands.getOperands(), rewriter, bb);
+    auto output = io.outputs[0];
+    RTLBuilder rtlb(op.getLoc(), rewriter);
+
+    // A winner is found if any of the two input valids are high.
+    Value hasWin = rtlb.bitOr(io.getInputValids());
+
+    // The winning index is either 0b0 (first) or 0b1 (second), hence we can
+    // just use either of the input valids as win index signal. The op is
+    // defined to select inputs with priority first >> second, so use the first
+    // input.
+    Value winWasFirst = io.inputs[0].valid;
+    Value winWasSecond = rtlb.bitNot(winWasFirst);
+    Value winIndex = winWasSecond;
+
+    output.valid->setValue(hasWin);
+    output.data->setValue(winIndex);
+
+    // Create the logic to set the done wires for the result. The done wire is
+    // asserted when the output is valid and ready.
+    Value outValidAndReady = rtlb.bitAnd({hasWin, output.ready});
+
+    // Create the logic to assign the arg ready outputs. An argument is ready
+    // when the output is valid and ready, and the given input is selected.
+    io.inputs[0].ready->setValue(rtlb.bitAnd({outValidAndReady, winWasFirst}));
+    io.inputs[1].ready->setValue(rtlb.bitAnd({outValidAndReady, winWasSecond}));
+
+    rewriter.replaceOp(op, output.channel);
+
+    return success();
+  }
+};
+
 class ToESIConversionPattern : public OpConversionPattern<ToESIOp> {
   // Essentially a no-op, seeing as the type converter does the heavy
   // lifting here.
@@ -848,13 +888,12 @@ class DCToHWPass : public DCToHWBase<DCToHWPass> {
 
     RewritePatternSet patterns(parent->getContext());
 
-    patterns.insert<ForkConversionPattern, JoinConversionPattern,
-                    SelectConversionPattern, BranchConversionPattern,
-                    PackConversionPattern, UnpackConversionPattern,
-                    BufferConversionPattern, SourceConversionPattern,
-                    SinkConversionPattern, TypeConversionPattern,
-                    ToESIConversionPattern, FromESIConversionPattern>(
-        typeConverter, parent->getContext());
+    patterns.insert<
+        ForkConversionPattern, JoinConversionPattern, SelectConversionPattern,
+        BranchConversionPattern, PackConversionPattern, UnpackConversionPattern,
+        BufferConversionPattern, SourceConversionPattern, SinkConversionPattern,
+        MergeConversionPattern, TypeConversionPattern, ToESIConversionPattern,
+        FromESIConversionPattern>(typeConverter, parent->getContext());
 
     if (failed(applyPartialConversion(parent, target, std::move(patterns))))
       signalPassFailure();

lib/Conversion/HandshakeToDC/HandshakeToDC.cpp

@@ -198,6 +198,50 @@ class JoinOpConversion : public DCOpConversionPattern<handshake::JoinOp> {
   }
 };
 
+class MergeOpConversion : public DCOpConversionPattern<handshake::MergeOp> {
+public:
+  using DCOpConversionPattern<handshake::MergeOp>::DCOpConversionPattern;
+  using OpAdaptor = typename handshake::MergeOp::Adaptor;
+
+  LogicalResult
+  matchAndRewrite(handshake::MergeOp op, OpAdaptor adaptor,
+                  ConversionPatternRewriter &rewriter) const override {
+    if (op.getNumOperands() > 2)
+      return op.emitOpError("only two inputs supported");
+
+    llvm::SmallVector<Value, 4> tokens, data;
+
+    for (auto input : adaptor.getDataOperands()) {
+      auto up = unpack(rewriter, input);
+      tokens.push_back(up.token);
+      if (up.data)
+        data.push_back(up.data);
+    }
+
+    // Control side
+    Value selectedIndex = rewriter.create<dc::MergeOp>(op.getLoc(), tokens);
+    auto selectedIndexUnpacked = unpack(rewriter, selectedIndex);
+    Value mergeOutput;
+
+    if (!data.empty()) {
+      // Data-merge; mux the selected input.
+      auto dataMux = rewriter.create<arith::SelectOp>(
+          op.getLoc(), selectedIndexUnpacked.data, data[0], data[1]);
+      convertedOps->insert(dataMux);
+
+      // Pack the data mux with the control token.
+      mergeOutput = pack(rewriter, selectedIndexUnpacked.token, dataMux);
+    } else {
+      // Control-only merge; throw away the index value of the dc.merge
+      // operation and only forward the dc.token.
+      mergeOutput = selectedIndexUnpacked.token;
+    }
+
+    rewriter.replaceOp(op, mergeOutput);
+    return success();
+  }
+};
+
 class ControlMergeOpConversion
     : public DCOpConversionPattern<handshake::ControlMergeOp> {
 public:
@@ -611,12 +655,12 @@ LogicalResult circt::handshaketodc::runHandshakeToDC(
   // Add handshake conversion patterns.
   // Note: merge/control merge are not supported - these are non-deterministic
   // operators and we do not care for them.
-  patterns
-      .add<BufferOpConversion, CondBranchConversionPattern,
-           SinkOpConversionPattern, SourceOpConversionPattern,
-           MuxOpConversionPattern, ForkOpConversionPattern, JoinOpConversion,
-           ControlMergeOpConversion, ConstantOpConversion, SyncOpConversion>(
-          ctx, typeConverter, &convertedOps);
+  patterns.add<BufferOpConversion, CondBranchConversionPattern,
+               SinkOpConversionPattern, SourceOpConversionPattern,
+               MuxOpConversionPattern, ForkOpConversionPattern,
+               JoinOpConversion, MergeOpConversion, ControlMergeOpConversion,
+               ConstantOpConversion, SyncOpConversion>(ctx, typeConverter,
+                                                       &convertedOps);
 
   // ALL other single-result operations are converted via the
   // UnitRateConversionPattern.

test/Conversion/DCToHW/basic.mlir

@@ -176,4 +176,23 @@ hw.module @sink(in %token : !dc.token) {
 hw.module @source(out token : !dc.token) {
     %token = dc.source
     hw.output %token : !dc.token
-}
+}
+
+// CHECK-LABEL:   hw.module @merge(in 
+// CHECK-SAME:                        %[[VAL_0:.*]] : !esi.channel<i0>, in
+// CHECK-SAME:                        %[[VAL_1:.*]] : !esi.channel<i0>, out token : !esi.channel<i1>) {
+// CHECK:           %[[VAL_2:.*]], %[[VAL_3:.*]] = esi.unwrap.vr %[[VAL_0]], %[[VAL_4:.*]] : i0
+// CHECK:           %[[VAL_5:.*]], %[[VAL_6:.*]] = esi.unwrap.vr %[[VAL_1]], %[[VAL_7:.*]] : i0
+// CHECK:           %[[VAL_8:.*]], %[[VAL_9:.*]] = esi.wrap.vr %[[VAL_10:.*]], %[[VAL_11:.*]] : i1
+// CHECK:           %[[VAL_11]] = comb.or %[[VAL_3]], %[[VAL_6]] : i1
+// CHECK:           %[[VAL_12:.*]] = hw.constant true
+// CHECK:           %[[VAL_10]] = comb.xor %[[VAL_3]], %[[VAL_12]] : i1
+// CHECK:           %[[VAL_13:.*]] = comb.and %[[VAL_11]], %[[VAL_9]] : i1
+// CHECK:           %[[VAL_4]] = comb.and %[[VAL_13]], %[[VAL_3]] : i1
+// CHECK:           %[[VAL_7]] = comb.and %[[VAL_13]], %[[VAL_10]] : i1
+// CHECK:           hw.output %[[VAL_8]] : !esi.channel<i1>
+// CHECK:         }
+hw.module @merge(in %first : !dc.token, in %second : !dc.token, out token : !dc.value<i1>) {
+    %selected = dc.merge %first, %second
+    hw.output %selected : !dc.value<i1>
+}

test/Conversion/HandshakeToDC/basic.mlir

@@ -177,3 +177,27 @@ handshake.func @branch_and_merge(%0 : i1, %1 : none) -> (none, index) {
   %true, %false = cond_br %0, %1 : none
   return %out, %idx : none, index
 }
+
+// CHECK:   hw.module @datamerge(in %[[VAL_0:.*]] : !dc.value<i1>, in %[[VAL_1:.*]] : !dc.value<i1>, in %[[VAL_2:.*]] : !dc.value<i1>, out out0 : !dc.value<i1>) {
+// CHECK:           %[[VAL_3:.*]], %[[VAL_4:.*]] = dc.unpack %[[VAL_0]] : !dc.value<i1>
+// CHECK:           %[[VAL_5:.*]], %[[VAL_6:.*]] = dc.unpack %[[VAL_1]] : !dc.value<i1>
+// CHECK:           %[[VAL_7:.*]] = dc.merge %[[VAL_3]], %[[VAL_5]]
+// CHECK:           %[[VAL_8:.*]], %[[VAL_9:.*]] = dc.unpack %[[VAL_7]] : !dc.value<i1>
+// CHECK:           %[[VAL_10:.*]] = arith.select %[[VAL_9]], %[[VAL_4]], %[[VAL_6]] : i1
+// CHECK:           %[[VAL_11:.*]] = dc.pack %[[VAL_8]], %[[VAL_10]] : i1
+// CHECK:           hw.output %[[VAL_11]] : !dc.value<i1>
+// CHECK:         }
+handshake.func @datamerge(%arg0 : i1, %arg1 : i1, %arg2 : i1) -> i1 {
+  %out = merge %arg0, %arg1 : i1
+  return %out : i1
+}
+
+// CHECK:   hw.module @nonemerge(in %[[VAL_0:.*]] : !dc.token, in %[[VAL_1:.*]] : !dc.token, out out0 : !dc.token) {
+// CHECK:           %[[VAL_2:.*]] = dc.merge %[[VAL_0]], %[[VAL_1]]
+// CHECK:           %[[VAL_3:.*]], %[[VAL_4:.*]] = dc.unpack %[[VAL_2]] : !dc.value<i1>
+// CHECK:           hw.output %[[VAL_3]] : !dc.token
+// CHECK:         }
+handshake.func @nonemerge(%arg0 : none, %arg1 : none) -> none {
+  %out = merge %arg0, %arg1 : none
+  return %out : none
+}