[FIRRTL][SFCCompat] Fix tests and handling of fullasyncreset on non-port.

lib/Dialect/FIRRTL/Transforms/SFCCompat.cpp

@@ -46,13 +46,21 @@ void SFCCompatPass::runOnOperation() {
   bool madeModifications = false;
   SmallVector<InvalidValueOp> invalidOps;
 
-  bool fullAsyncResetExists = false;
-  AnnotationSet::removePortAnnotations(
+  auto fullAsyncResetAttr =
+      StringAttr::get(&getContext(), fullAsyncResetAnnoClass);
+  auto isFullAsyncResetAnno = [fullAsyncResetAttr](Annotation anno) {
+    return anno.getClassAttr() == fullAsyncResetAttr;
+  };
+  bool fullAsyncResetExists = AnnotationSet::removePortAnnotations(
       getOperation(), [&](unsigned argNum, Annotation anno) {
-        if (!anno.isClass(fullAsyncResetAnnoClass))
-          return false;
-        return fullAsyncResetExists = true;
+        return isFullAsyncResetAnno(anno);
       });
+  getOperation()->walk(
+      [isFullAsyncResetAnno, &fullAsyncResetExists](Operation *op) {
+        fullAsyncResetExists |=
+            AnnotationSet::removeAnnotations(op, isFullAsyncResetAnno);
+      });
+  madeModifications |= fullAsyncResetExists;
 
   auto result = getOperation()->walk([&](Operation *op) {
     // Populate invalidOps for later handling.

test/firtool/async-reset-anno.fir

@@ -1,14 +1,17 @@
-; RUN: firtool %s -parse-only | circt-opt -firrtl-infer-resets | FileCheck %s --check-prefix POST-INFER-RESETS
-; RUN: firtool %s -parse-only | circt-opt -firrtl-infer-resets -firrtl-sfc-compat | FileCheck %s --implicit-check-not POST-SFC-COMPAT-NOT
+; RUN: firtool %s -parse-only | circt-opt -pass-pipeline='builtin.module(firrtl.circuit(firrtl-infer-resets))'  | FileCheck %s --check-prefixes COMMON,POST-INFER-RESETS
+; RUN: firtool %s -parse-only | circt-opt -pass-pipeline='builtin.module(firrtl.circuit(firrtl-infer-resets,firrtl.module(firrtl-sfc-compat)))' | FileCheck %s --check-prefixes COMMON,POST-SFC-COMPAT
 
 ; Check that FullAsyncResetAnnotation exists after infer-resets pass
 ; but is deleted after sfc-compat
 
 FIRRTL version 3.3.0
-circuit test :%[[{
-  "class":"sifive.enterprise.firrtl.FullAsyncResetAnnotation",
-    "target":"~test|test>reset"
-    }]]
+circuit test :%[[
+{ "class":"sifive.enterprise.firrtl.FullAsyncResetAnnotation",
+  "target":"~test|test>reset" },
+{ "class":"sifive.enterprise.firrtl.FullAsyncResetAnnotation",
+  "target":"~test|foo>r" }
+]]
+  ; COMMON-LABEL: module @test
   module test :
     input clock : Clock
     input reset : AsyncReset
@@ -17,3 +20,15 @@ circuit test :%[[{
     input in : { foo : UInt<8>, bar : UInt<8>}
     output out : { foo : UInt<8>, bar : UInt<8>}
     connect out, in
+
+  ; COMMON-LABEL: module private @foo
+  module foo :
+    input clock : Clock
+    input reset : AsyncReset
+    input in : { foo : UInt<8>, bar : UInt<8>}
+    output out : { foo : UInt<8>, bar : UInt<8>}
+
+    ; POST-INFER-RESETS: [{class = "sifive.enterprise.firrtl.FullAsyncResetAnnotation"}]
+    ; POST-SFC-COMPAT-NOT: [{class = "sifive.enterprise.firrtl.FullAsyncResetAnnotation"}]
+     wire r : AsyncReset
+    connect out, in

test/firtool/async-reset.fir

@@ -1,6 +1,7 @@
-; RUN: firtool %s | FileCheck %s
+; RUN: firtool --split-input-file %s | FileCheck %s
 
 FIRRTL version 3.3.0
+; CHECK-LABEL: module test(
 circuit test :%[[{
   "class":"sifive.enterprise.firrtl.FullAsyncResetAnnotation",
     "target":"~test|test>reset"
@@ -25,3 +26,33 @@ circuit test :%[[{
     connect reg1, in
     connect reg2, reg1
     connect out, reg2
+
+;// -----
+; CHECK-LABEL: module test_wire(
+FIRRTL version 3.3.0
+circuit test_wire :%[[{
+  "class":"sifive.enterprise.firrtl.FullAsyncResetAnnotation",
+    "target":"~test_wire|test_wire>reset"
+  }]]
+  module test_wire :
+    input clock : Clock
+    input r : AsyncReset
+    input in : { foo : UInt<8>, bar : UInt<8>}
+    output out : { foo : UInt<8>, bar : UInt<8>}
+
+    node reset = r
+
+    wire reg1_w : { foo : UInt<8>, bar : UInt<8>}
+    invalidate reg1_w.bar
+    invalidate reg1_w.foo
+    ; CHECK: reg1_foo <= 8'hC;
+    ; CHECK: reg1_bar <= 8'h0;
+    connect reg1_w.foo, UInt<8>(0hc)
+    invalidate reg1_w.bar
+    ; CHECK: reg1_foo = 8'hC;
+    ; CHECK: reg1_bar = 8'h0;
+    regreset reg1 : { foo : UInt<8>, bar : UInt<8>}, clock, reset, reg1_w
+    wire reg2 : { foo : UInt<8>, bar : UInt<8>}
+    connect reg1, in
+    connect reg2, reg1
+    connect out, reg2