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[SV] Add sv.reserve_names op to disallow names #7024

Merged
merged 2 commits into from
May 14, 2024
Merged

[SV] Add sv.reserve_names op to disallow names #7024

merged 2 commits into from
May 14, 2024

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teqdruid
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Introduce an op to specific a list of names which Export Verilog should never use anywhere. Applies to module names, port names, reg/wire/logic names, etc.

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[SV] Add sv.reserve_names op to disallow names
e6fc9d9 
Introduce an op to specific a list of names which Export Verilog should
never use anywhere. Applies to module names, port names, reg/wire/logic
names, etc.
@teqdruid teqdruid added the Verilog/SystemVerilog Involving a Verilog dialect label May 11, 2024
uenoku
uenoku reviewed May 13, 2024
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It makes sense to me to define it as an op. Alternatively we could implement it as a lowering option to disallow specific names but it would be more flexible to import names from op.

lib/Conversion/ExportVerilog/ExportVerilogInternals.h Outdated Show resolved Hide resolved
include/circt/Dialect/SV/SVStatements.td Outdated Show resolved Hide resolved
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@uenoku at the last ODM we agreed it should be an op which lives at the top level.

@teqdruid teqdruid requested a review from uenoku May 13, 2024 19:30
uenoku
uenoku approved these changes May 14, 2024
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LGTM

@teqdruid teqdruid merged commit f1a822e into main May 14, 2024
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@teqdruid teqdruid deleted the teqdruid/sv-reserve-name branch May 14, 2024 02:53
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@uenoku uenoku uenoku approved these changes

@dtzSiFive dtzSiFive Awaiting requested review from dtzSiFive

@darthscsi darthscsi Awaiting requested review from darthscsi darthscsi is a code owner

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@teqdruid @uenoku