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[DAG] Remove oneuse check in select_cc setgt X, -1, C, ~C fold
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This appears to produce better code, even if the condition may need to
be replicated.
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@davemgreen
davemgreen committed Sep 5, 2021
1 parent f114ef3 commit 1b83aaa
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Showing 10 changed files with 118 additions and 147 deletions.
3 changes: 1 addition & 2 deletions llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -22881,8 +22881,7 @@ SDValue DAGCombiner::SimplifySelectCC(const SDLoc &DL, SDValue N0, SDValue N1,
N2C->getAPIntValue() == ~N3C->getAPIntValue() &&
((N1C->isAllOnesValue() && CC == ISD::SETGT) ||
(N1C->isNullValue() && CC == ISD::SETLT)) &&
!TLI.shouldAvoidTransformToShift(VT, CmpOpVT.getScalarSizeInBits() - 1) &&
N0->hasOneUse()) {
!TLI.shouldAvoidTransformToShift(VT, CmpOpVT.getScalarSizeInBits() - 1)) {
SDValue ASR = DAG.getNode(
ISD::SRA, DL, CmpOpVT, N0,
DAG.getConstant(CmpOpVT.getScalarSizeInBits() - 1, DL, CmpOpVT));
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AArch64/select-constant-xor.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -198,9 +198,9 @@ define i32 @selecti32i32_sgt(i32 %a) {
define i32 @oneusecmp(i32 %a, i32 %b, i32 %d) {
; CHECK-LABEL: oneusecmp:
; CHECK: // %bb.0:
; CHECK-NEXT: asr w8, w0, #31
; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: mov w8, #-128
; CHECK-NEXT: cinv w8, w8, ge
; CHECK-NEXT: eor w8, w8, #0x7f
; CHECK-NEXT: csel w9, w2, w1, lt
; CHECK-NEXT: add w0, w8, w9
; CHECK-NEXT: ret
Expand Down
69 changes: 31 additions & 38 deletions llvm/test/CodeGen/AMDGPU/fp_to_sint.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -237,7 +237,7 @@ define amdgpu_kernel void @fp_to_sint_i64 (i64 addrspace(1)* %out, float %in) {
;
; EG-LABEL: fp_to_sint_i64:
; EG: ; %bb.0: ; %entry
; EG-NEXT: ALU 41, @4, KC0[CB0:0-32], KC1[]
; EG-NEXT: ALU 40, @4, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
; EG-NEXT: CF_END
; EG-NEXT: PAD
Expand Down Expand Up @@ -277,11 +277,10 @@ define amdgpu_kernel void @fp_to_sint_i64 (i64 addrspace(1)* %out, float %in) {
; EG-NEXT: SUB_INT T2.W, PS, T1.W,
; EG-NEXT: SUBB_UINT * T3.W, PV.W, T1.W,
; EG-NEXT: SUB_INT T2.W, PV.W, PS,
; EG-NEXT: SETGT_INT * T3.W, T0.X, literal.x,
; EG-NEXT: -1(nan), 0(0.000000e+00)
; EG-NEXT: CNDE_INT T0.Y, PS, 0.0, PV.W,
; EG-NEXT: SETGT_INT * T3.W, 0.0, T0.X,
; EG-NEXT: CNDE_INT T0.Y, PS, PV.W, 0.0,
; EG-NEXT: SUB_INT * T0.W, T0.W, T1.W,
; EG-NEXT: CNDE_INT T0.X, T3.W, 0.0, PV.W,
; EG-NEXT: CNDE_INT T0.X, T3.W, PV.W, 0.0,
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
entry:
Expand Down Expand Up @@ -361,7 +360,7 @@ define amdgpu_kernel void @fp_to_sint_v2i64(<2 x i64> addrspace(1)* %out, <2 x f
;
; EG-LABEL: fp_to_sint_v2i64:
; EG: ; %bb.0:
; EG-NEXT: ALU 77, @4, KC0[CB0:0-32], KC1[]
; EG-NEXT: ALU 75, @4, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T0.X, 1
; EG-NEXT: CF_END
; EG-NEXT: PAD
Expand Down Expand Up @@ -429,19 +428,17 @@ define amdgpu_kernel void @fp_to_sint_v2i64(<2 x i64> addrspace(1)* %out, <2 x f
; EG-NEXT: SUB_INT T0.W, PV.Y, T2.W,
; EG-NEXT: SUBB_UINT * T4.W, PV.X, T2.W,
; EG-NEXT: SUB_INT T1.Y, PV.W, PS,
; EG-NEXT: SETGT_INT T1.Z, T3.Y, literal.x,
; EG-NEXT: SETGT_INT T1.Z, 0.0, T3.Y,
; EG-NEXT: SUB_INT T0.W, PV.Z, T3.W,
; EG-NEXT: SUBB_UINT * T4.W, PV.Y, T3.W,
; EG-NEXT: -1(nan), 0(0.000000e+00)
; EG-NEXT: SUB_INT T0.Z, PV.W, PS,
; EG-NEXT: SETGT_INT T0.W, T1.W, literal.x,
; EG-NEXT: CNDE_INT * T1.W, PV.Z, 0.0, PV.Y, BS:VEC_021/SCL_122
; EG-NEXT: -1(nan), 0(0.000000e+00)
; EG-NEXT: CNDE_INT T1.Y, PV.W, 0.0, PV.Z,
; EG-NEXT: SETGT_INT T0.W, 0.0, T1.W,
; EG-NEXT: CNDE_INT * T1.W, PV.Z, PV.Y, 0.0,
; EG-NEXT: CNDE_INT T1.Y, PV.W, PV.Z, 0.0,
; EG-NEXT: SUB_INT * T2.W, T0.X, T2.W,
; EG-NEXT: CNDE_INT T1.Z, T1.Z, 0.0, PV.W,
; EG-NEXT: CNDE_INT T1.Z, T1.Z, PV.W, 0.0,
; EG-NEXT: SUB_INT * T2.W, T0.Y, T3.W,
; EG-NEXT: CNDE_INT T1.X, T0.W, 0.0, PV.W,
; EG-NEXT: CNDE_INT T1.X, T0.W, PV.W, 0.0,
; EG-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%conv = fptosi <2 x float> %x to <2 x i64>
Expand Down Expand Up @@ -567,7 +564,7 @@ define amdgpu_kernel void @fp_to_sint_v4i64(<4 x i64> addrspace(1)* %out, <4 x f
; EG-LABEL: fp_to_sint_v4i64:
; EG: ; %bb.0:
; EG-NEXT: ALU 101, @6, KC0[CB0:0-32], KC1[]
; EG-NEXT: ALU 58, @108, KC0[CB0:0-32], KC1[]
; EG-NEXT: ALU 54, @108, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.XYZW, T0.X, 0
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T6.XYZW, T2.X, 1
; EG-NEXT: CF_END
Expand Down Expand Up @@ -653,12 +650,11 @@ define amdgpu_kernel void @fp_to_sint_v4i64(<4 x i64> addrspace(1)* %out, <4 x f
; EG-NEXT: SUBB_UINT * T3.W, PV.Y, T2.W,
; EG-NEXT: 8388607(1.175494e-38), 32(4.484155e-44)
; EG-NEXT: SUB_INT T5.X, PV.W, PS,
; EG-NEXT: SETGT_INT T0.Y, T0.Y, literal.x,
; EG-NEXT: SETGT_INT T0.Y, 0.0, T0.Y,
; EG-NEXT: CNDE_INT T0.Z, PV.Y, PV.Z, 0.0,
; EG-NEXT: OR_INT T1.W, PV.X, literal.y,
; EG-NEXT: ADD_INT * T3.W, T3.X, literal.z,
; EG-NEXT: -1(nan), 8388608(1.175494e-38)
; EG-NEXT: -150(nan), 0(0.000000e+00)
; EG-NEXT: OR_INT T1.W, PV.X, literal.x,
; EG-NEXT: ADD_INT * T3.W, T3.X, literal.y,
; EG-NEXT: 8388608(1.175494e-38), -150(nan)
; EG-NEXT: ADD_INT T4.X, T3.X, literal.x,
; EG-NEXT: SUB_INT T3.Y, literal.y, T3.X,
; EG-NEXT: AND_INT T2.Z, PS, literal.z,
Expand All @@ -673,15 +669,15 @@ define amdgpu_kernel void @fp_to_sint_v4i64(<4 x i64> addrspace(1)* %out, <4 x f
; EG-NEXT: AND_INT * T3.W, PV.Y, literal.x,
; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
; EG-NEXT: ADD_INT T6.X, T1.X, literal.x,
; EG-NEXT: CNDE_INT * T3.Y, PS, PV.W, 0.0,
; EG-NEXT: CNDE_INT T3.Y, PS, PV.W, 0.0,
; EG-NEXT: CNDE_INT * T3.Z, PV.Z, PV.Y, 0.0,
; EG-NEXT: -150(nan), 0(0.000000e+00)
; EG-NEXT: ALU clause starting at 108:
; EG-NEXT: CNDE_INT T3.Z, T2.Z, T4.Y, 0.0,
; EG-NEXT: CNDE_INT T1.W, T2.Z, T3.X, T4.Y,
; EG-NEXT: SETGT_INT * T3.W, T4.X, literal.x,
; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00)
; EG-NEXT: CNDE_INT T3.X, PS, 0.0, PV.W,
; EG-NEXT: CNDE_INT T3.Y, PS, T3.Y, PV.Z,
; EG-NEXT: CNDE_INT T3.Y, PS, T3.Y, T3.Z,
; EG-NEXT: AND_INT T2.Z, T6.X, literal.x,
; EG-NEXT: NOT_INT T1.W, T6.X,
; EG-NEXT: LSHR * T3.W, T0.W, 1,
Expand All @@ -708,29 +704,26 @@ define amdgpu_kernel void @fp_to_sint_v4i64(<4 x i64> addrspace(1)* %out, <4 x f
; EG-NEXT: XOR_INT T1.X, PV.W, PS,
; EG-NEXT: XOR_INT T5.Y, PV.Z, PS,
; EG-NEXT: SUB_INT T0.Z, PV.X, PV.Y,
; EG-NEXT: SETGT_INT T1.W, T4.X, literal.x,
; EG-NEXT: CNDE_INT * T6.W, T0.Y, 0.0, T5.X, BS:VEC_021/SCL_122
; EG-NEXT: -1(nan), 0(0.000000e+00)
; EG-NEXT: SETGT_INT T0.X, T0.X, literal.x,
; EG-NEXT: CNDE_INT T6.Y, PV.W, 0.0, PV.Z,
; EG-NEXT: SETGT_INT T1.W, 0.0, T4.X, BS:VEC_021/SCL_122
; EG-NEXT: CNDE_INT * T6.W, T0.Y, T5.X, 0.0,
; EG-NEXT: SETGT_INT T0.X, 0.0, T0.X,
; EG-NEXT: CNDE_INT T6.Y, PV.W, PV.Z, 0.0,
; EG-NEXT: SUB_INT T0.Z, T1.Y, T2.W, BS:VEC_021/SCL_122
; EG-NEXT: SUB_INT T2.W, PV.Y, T3.W,
; EG-NEXT: SUBB_UINT * T4.W, PV.X, T3.W,
; EG-NEXT: -1(nan), 0(0.000000e+00)
; EG-NEXT: SUB_INT T3.X, PV.W, PS,
; EG-NEXT: SETGT_INT T1.Y, T4.Y, literal.x,
; EG-NEXT: CNDE_INT T6.Z, T0.Y, 0.0, PV.Z, BS:VEC_120/SCL_212
; EG-NEXT: SUB_INT T0.W, T0.W, T7.X,
; EG-NEXT: CNDE_INT * T4.W, PV.X, 0.0, T2.X, BS:VEC_021/SCL_122
; EG-NEXT: -1(nan), 0(0.000000e+00)
; EG-NEXT: CNDE_INT T6.X, T1.W, 0.0, PV.W,
; EG-NEXT: CNDE_INT T4.Y, PV.Y, 0.0, PV.X,
; EG-NEXT: SETGT_INT T1.Y, 0.0, T4.Y,
; EG-NEXT: CNDE_INT T6.Z, T0.Y, PV.Z, 0.0,
; EG-NEXT: SUB_INT T0.W, T0.W, T7.X, BS:VEC_021/SCL_122
; EG-NEXT: CNDE_INT * T4.W, PV.X, T2.X, 0.0,
; EG-NEXT: CNDE_INT T6.X, T1.W, PV.W, 0.0,
; EG-NEXT: CNDE_INT T4.Y, PV.Y, PV.X, 0.0,
; EG-NEXT: SUB_INT T0.W, T1.Z, T2.Y,
; EG-NEXT: LSHR * T2.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
; EG-NEXT: CNDE_INT T4.Z, T0.X, 0.0, PV.W,
; EG-NEXT: CNDE_INT T4.Z, T0.X, PV.W, 0.0,
; EG-NEXT: SUB_INT * T0.W, T1.X, T3.W, BS:VEC_120/SCL_212
; EG-NEXT: CNDE_INT T4.X, T1.Y, 0.0, PV.W,
; EG-NEXT: CNDE_INT T4.X, T1.Y, PV.W, 0.0,
; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,
; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
; EG-NEXT: LSHR * T0.X, PV.W, literal.x,
Expand Down
69 changes: 31 additions & 38 deletions llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -184,7 +184,7 @@ define amdgpu_kernel void @fp_to_uint_f32_to_i64(i64 addrspace(1)* %out, float %
;
; EG-LABEL: fp_to_uint_f32_to_i64:
; EG: ; %bb.0:
; EG-NEXT: ALU 41, @4, KC0[CB0:0-32], KC1[]
; EG-NEXT: ALU 40, @4, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
; EG-NEXT: CF_END
; EG-NEXT: PAD
Expand Down Expand Up @@ -224,11 +224,10 @@ define amdgpu_kernel void @fp_to_uint_f32_to_i64(i64 addrspace(1)* %out, float %
; EG-NEXT: SUB_INT T2.W, PS, T1.W,
; EG-NEXT: SUBB_UINT * T3.W, PV.W, T1.W,
; EG-NEXT: SUB_INT T2.W, PV.W, PS,
; EG-NEXT: SETGT_INT * T3.W, T0.X, literal.x,
; EG-NEXT: -1(nan), 0(0.000000e+00)
; EG-NEXT: CNDE_INT T0.Y, PS, 0.0, PV.W,
; EG-NEXT: SETGT_INT * T3.W, 0.0, T0.X,
; EG-NEXT: CNDE_INT T0.Y, PS, PV.W, 0.0,
; EG-NEXT: SUB_INT * T0.W, T0.W, T1.W,
; EG-NEXT: CNDE_INT T0.X, T3.W, 0.0, PV.W,
; EG-NEXT: CNDE_INT T0.X, T3.W, PV.W, 0.0,
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%conv = fptoui float %x to i64
Expand Down Expand Up @@ -287,7 +286,7 @@ define amdgpu_kernel void @fp_to_uint_v2f32_to_v2i64(<2 x i64> addrspace(1)* %ou
;
; EG-LABEL: fp_to_uint_v2f32_to_v2i64:
; EG: ; %bb.0:
; EG-NEXT: ALU 77, @4, KC0[CB0:0-32], KC1[]
; EG-NEXT: ALU 75, @4, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T0.X, 1
; EG-NEXT: CF_END
; EG-NEXT: PAD
Expand Down Expand Up @@ -355,19 +354,17 @@ define amdgpu_kernel void @fp_to_uint_v2f32_to_v2i64(<2 x i64> addrspace(1)* %ou
; EG-NEXT: SUB_INT T0.W, PV.Y, T2.W,
; EG-NEXT: SUBB_UINT * T4.W, PV.X, T2.W,
; EG-NEXT: SUB_INT T1.Y, PV.W, PS,
; EG-NEXT: SETGT_INT T1.Z, T3.Y, literal.x,
; EG-NEXT: SETGT_INT T1.Z, 0.0, T3.Y,
; EG-NEXT: SUB_INT T0.W, PV.Z, T3.W,
; EG-NEXT: SUBB_UINT * T4.W, PV.Y, T3.W,
; EG-NEXT: -1(nan), 0(0.000000e+00)
; EG-NEXT: SUB_INT T0.Z, PV.W, PS,
; EG-NEXT: SETGT_INT T0.W, T1.W, literal.x,
; EG-NEXT: CNDE_INT * T1.W, PV.Z, 0.0, PV.Y, BS:VEC_021/SCL_122
; EG-NEXT: -1(nan), 0(0.000000e+00)
; EG-NEXT: CNDE_INT T1.Y, PV.W, 0.0, PV.Z,
; EG-NEXT: SETGT_INT T0.W, 0.0, T1.W,
; EG-NEXT: CNDE_INT * T1.W, PV.Z, PV.Y, 0.0,
; EG-NEXT: CNDE_INT T1.Y, PV.W, PV.Z, 0.0,
; EG-NEXT: SUB_INT * T2.W, T0.X, T2.W,
; EG-NEXT: CNDE_INT T1.Z, T1.Z, 0.0, PV.W,
; EG-NEXT: CNDE_INT T1.Z, T1.Z, PV.W, 0.0,
; EG-NEXT: SUB_INT * T2.W, T0.Y, T3.W,
; EG-NEXT: CNDE_INT T1.X, T0.W, 0.0, PV.W,
; EG-NEXT: CNDE_INT T1.X, T0.W, PV.W, 0.0,
; EG-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%conv = fptoui <2 x float> %x to <2 x i64>
Expand Down Expand Up @@ -453,7 +450,7 @@ define amdgpu_kernel void @fp_to_uint_v4f32_to_v4i64(<4 x i64> addrspace(1)* %ou
; EG-LABEL: fp_to_uint_v4f32_to_v4i64:
; EG: ; %bb.0:
; EG-NEXT: ALU 101, @6, KC0[CB0:0-32], KC1[]
; EG-NEXT: ALU 58, @108, KC0[CB0:0-32], KC1[]
; EG-NEXT: ALU 54, @108, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.XYZW, T0.X, 0
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T6.XYZW, T2.X, 1
; EG-NEXT: CF_END
Expand Down Expand Up @@ -539,12 +536,11 @@ define amdgpu_kernel void @fp_to_uint_v4f32_to_v4i64(<4 x i64> addrspace(1)* %ou
; EG-NEXT: SUBB_UINT * T3.W, PV.Y, T2.W,
; EG-NEXT: 8388607(1.175494e-38), 32(4.484155e-44)
; EG-NEXT: SUB_INT T5.X, PV.W, PS,
; EG-NEXT: SETGT_INT T0.Y, T0.Y, literal.x,
; EG-NEXT: SETGT_INT T0.Y, 0.0, T0.Y,
; EG-NEXT: CNDE_INT T0.Z, PV.Y, PV.Z, 0.0,
; EG-NEXT: OR_INT T1.W, PV.X, literal.y,
; EG-NEXT: ADD_INT * T3.W, T3.X, literal.z,
; EG-NEXT: -1(nan), 8388608(1.175494e-38)
; EG-NEXT: -150(nan), 0(0.000000e+00)
; EG-NEXT: OR_INT T1.W, PV.X, literal.x,
; EG-NEXT: ADD_INT * T3.W, T3.X, literal.y,
; EG-NEXT: 8388608(1.175494e-38), -150(nan)
; EG-NEXT: ADD_INT T4.X, T3.X, literal.x,
; EG-NEXT: SUB_INT T3.Y, literal.y, T3.X,
; EG-NEXT: AND_INT T2.Z, PS, literal.z,
Expand All @@ -559,15 +555,15 @@ define amdgpu_kernel void @fp_to_uint_v4f32_to_v4i64(<4 x i64> addrspace(1)* %ou
; EG-NEXT: AND_INT * T3.W, PV.Y, literal.x,
; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
; EG-NEXT: ADD_INT T6.X, T1.X, literal.x,
; EG-NEXT: CNDE_INT * T3.Y, PS, PV.W, 0.0,
; EG-NEXT: CNDE_INT T3.Y, PS, PV.W, 0.0,
; EG-NEXT: CNDE_INT * T3.Z, PV.Z, PV.Y, 0.0,
; EG-NEXT: -150(nan), 0(0.000000e+00)
; EG-NEXT: ALU clause starting at 108:
; EG-NEXT: CNDE_INT T3.Z, T2.Z, T4.Y, 0.0,
; EG-NEXT: CNDE_INT T1.W, T2.Z, T3.X, T4.Y,
; EG-NEXT: SETGT_INT * T3.W, T4.X, literal.x,
; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00)
; EG-NEXT: CNDE_INT T3.X, PS, 0.0, PV.W,
; EG-NEXT: CNDE_INT T3.Y, PS, T3.Y, PV.Z,
; EG-NEXT: CNDE_INT T3.Y, PS, T3.Y, T3.Z,
; EG-NEXT: AND_INT T2.Z, T6.X, literal.x,
; EG-NEXT: NOT_INT T1.W, T6.X,
; EG-NEXT: LSHR * T3.W, T0.W, 1,
Expand All @@ -594,29 +590,26 @@ define amdgpu_kernel void @fp_to_uint_v4f32_to_v4i64(<4 x i64> addrspace(1)* %ou
; EG-NEXT: XOR_INT T1.X, PV.W, PS,
; EG-NEXT: XOR_INT T5.Y, PV.Z, PS,
; EG-NEXT: SUB_INT T0.Z, PV.X, PV.Y,
; EG-NEXT: SETGT_INT T1.W, T4.X, literal.x,
; EG-NEXT: CNDE_INT * T6.W, T0.Y, 0.0, T5.X, BS:VEC_021/SCL_122
; EG-NEXT: -1(nan), 0(0.000000e+00)
; EG-NEXT: SETGT_INT T0.X, T0.X, literal.x,
; EG-NEXT: CNDE_INT T6.Y, PV.W, 0.0, PV.Z,
; EG-NEXT: SETGT_INT T1.W, 0.0, T4.X, BS:VEC_021/SCL_122
; EG-NEXT: CNDE_INT * T6.W, T0.Y, T5.X, 0.0,
; EG-NEXT: SETGT_INT T0.X, 0.0, T0.X,
; EG-NEXT: CNDE_INT T6.Y, PV.W, PV.Z, 0.0,
; EG-NEXT: SUB_INT T0.Z, T1.Y, T2.W, BS:VEC_021/SCL_122
; EG-NEXT: SUB_INT T2.W, PV.Y, T3.W,
; EG-NEXT: SUBB_UINT * T4.W, PV.X, T3.W,
; EG-NEXT: -1(nan), 0(0.000000e+00)
; EG-NEXT: SUB_INT T3.X, PV.W, PS,
; EG-NEXT: SETGT_INT T1.Y, T4.Y, literal.x,
; EG-NEXT: CNDE_INT T6.Z, T0.Y, 0.0, PV.Z, BS:VEC_120/SCL_212
; EG-NEXT: SUB_INT T0.W, T0.W, T7.X,
; EG-NEXT: CNDE_INT * T4.W, PV.X, 0.0, T2.X, BS:VEC_021/SCL_122
; EG-NEXT: -1(nan), 0(0.000000e+00)
; EG-NEXT: CNDE_INT T6.X, T1.W, 0.0, PV.W,
; EG-NEXT: CNDE_INT T4.Y, PV.Y, 0.0, PV.X,
; EG-NEXT: SETGT_INT T1.Y, 0.0, T4.Y,
; EG-NEXT: CNDE_INT T6.Z, T0.Y, PV.Z, 0.0,
; EG-NEXT: SUB_INT T0.W, T0.W, T7.X, BS:VEC_021/SCL_122
; EG-NEXT: CNDE_INT * T4.W, PV.X, T2.X, 0.0,
; EG-NEXT: CNDE_INT T6.X, T1.W, PV.W, 0.0,
; EG-NEXT: CNDE_INT T4.Y, PV.Y, PV.X, 0.0,
; EG-NEXT: SUB_INT T0.W, T1.Z, T2.Y,
; EG-NEXT: LSHR * T2.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
; EG-NEXT: CNDE_INT T4.Z, T0.X, 0.0, PV.W,
; EG-NEXT: CNDE_INT T4.Z, T0.X, PV.W, 0.0,
; EG-NEXT: SUB_INT * T0.W, T1.X, T3.W, BS:VEC_120/SCL_212
; EG-NEXT: CNDE_INT T4.X, T1.Y, 0.0, PV.W,
; EG-NEXT: CNDE_INT T4.X, T1.Y, PV.W, 0.0,
; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,
; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
; EG-NEXT: LSHR * T0.X, PV.W, literal.x,
Expand Down
7 changes: 3 additions & 4 deletions llvm/test/CodeGen/AMDGPU/selectcc-icmp-select-float.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@ define amdgpu_kernel void @test(float addrspace(1)* %out, i32 addrspace(1)* %in)
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
; CHECK-NEXT: TEX 0 @6
; CHECK-NEXT: ALU 4, @9, KC0[CB0:0-32], KC1[]
; CHECK-NEXT: ALU 3, @9, KC0[CB0:0-32], KC1[]
; CHECK-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
; CHECK-NEXT: CF_END
; CHECK-NEXT: PAD
Expand All @@ -17,9 +17,8 @@ define amdgpu_kernel void @test(float addrspace(1)* %out, i32 addrspace(1)* %in)
; CHECK-NEXT: ALU clause starting at 8:
; CHECK-NEXT: MOV * T0.X, KC0[2].Z,
; CHECK-NEXT: ALU clause starting at 9:
; CHECK-NEXT: SETGT_INT * T0.W, T0.X, literal.x,
; CHECK-NEXT: -1(nan), 0(0.000000e+00)
; CHECK-NEXT: CNDE_INT T0.X, PV.W, 0.0, literal.x,
; CHECK-NEXT: SETGT_INT * T0.W, 0.0, T0.X,
; CHECK-NEXT: CNDE_INT T0.X, PV.W, literal.x, 0.0,
; CHECK-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,
; CHECK-NEXT: 1065353216(1.000000e+00), 2(2.802597e-45)
entry:
Expand Down
22 changes: 9 additions & 13 deletions llvm/test/CodeGen/ARM/select-constant-xor.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -358,9 +358,9 @@ define i32 @oneusecmp(i32 %a, i32 %b, i32 %d) {
; CHECK7A-LABEL: oneusecmp:
; CHECK7A: @ %bb.0:
; CHECK7A-NEXT: cmp r0, #0
; CHECK7A-NEXT: mov r0, #127
; CHECK7A-NEXT: mvnmi r0, #127
; CHECK7A-NEXT: movmi r1, r2
; CHECK7A-NEXT: mov r2, #127
; CHECK7A-NEXT: eor r0, r2, r0, asr #31
; CHECK7A-NEXT: add r0, r0, r1
; CHECK7A-NEXT: bx lr
;
Expand All @@ -371,32 +371,28 @@ define i32 @oneusecmp(i32 %a, i32 %b, i32 %d) {
; CHECK6M-NEXT: @ %bb.1:
; CHECK6M-NEXT: mov r2, r1
; CHECK6M-NEXT: .LBB10_2:
; CHECK6M-NEXT: asrs r0, r0, #31
; CHECK6M-NEXT: movs r1, #127
; CHECK6M-NEXT: cmp r0, #0
; CHECK6M-NEXT: bpl .LBB10_4
; CHECK6M-NEXT: @ %bb.3:
; CHECK6M-NEXT: mvns r1, r1
; CHECK6M-NEXT: .LBB10_4:
; CHECK6M-NEXT: eors r1, r0
; CHECK6M-NEXT: adds r0, r1, r2
; CHECK6M-NEXT: bx lr
;
; CHECK7M-LABEL: oneusecmp:
; CHECK7M: @ %bb.0:
; CHECK7M-NEXT: cmp r0, #0
; CHECK7M-NEXT: mov.w r0, #127
; CHECK7M-NEXT: it mi
; CHECK7M-NEXT: movmi r1, r2
; CHECK7M-NEXT: it mi
; CHECK7M-NEXT: mvnmi r0, #127
; CHECK7M-NEXT: movs r2, #127
; CHECK7M-NEXT: eor.w r0, r2, r0, asr #31
; CHECK7M-NEXT: add r0, r1
; CHECK7M-NEXT: bx lr
;
; CHECK81M-LABEL: oneusecmp:
; CHECK81M: @ %bb.0:
; CHECK81M-NEXT: cmp r0, #0
; CHECK81M-NEXT: csel r0, r2, r1, mi
; CHECK81M-NEXT: mov.w r1, #127
; CHECK81M-NEXT: cinv r1, r1, mi
; CHECK81M-NEXT: csel r1, r2, r1, mi
; CHECK81M-NEXT: movs r2, #127
; CHECK81M-NEXT: eor.w r0, r2, r0, asr #31
; CHECK81M-NEXT: add r0, r1
; CHECK81M-NEXT: bx lr
%c = icmp sle i32 %a, -1
Expand Down
5 changes: 2 additions & 3 deletions llvm/test/CodeGen/PowerPC/select-constant-xor.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -129,10 +129,9 @@ define i32 @icmpasrne(i32 %input, i32 %a, i32 %b) {
define i32 @oneusecmp(i32 %a, i32 %b, i32 %d) {
; CHECK-LABEL: oneusecmp:
; CHECK: # %bb.0:
; CHECK-NEXT: li 6, 127
; CHECK-NEXT: srawi 6, 3, 31
; CHECK-NEXT: cmpwi 3, 0
; CHECK-NEXT: li 3, -128
; CHECK-NEXT: isellt 3, 3, 6
; CHECK-NEXT: xori 3, 6, 127
; CHECK-NEXT: isellt 4, 5, 4
; CHECK-NEXT: add 3, 3, 4
; CHECK-NEXT: blr
Expand Down
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