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[CodeGen] Use MCRegister for CCState::AllocateReg and CCValAssign::ge…
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…tReg. NFC (#106032)
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@topperc
topperc authored Aug 26, 2024
1 parent d88876e commit 4b0c0ec
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Showing 11 changed files with 55 additions and 55 deletions.
12 changes: 6 additions & 6 deletions llvm/include/llvm/CodeGen/CallingConvLower.h
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Original file line number Diff line number Diff line change
Expand Up @@ -81,16 +81,16 @@ class CCValAssign {
}

public:
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo,
static CCValAssign getReg(unsigned ValNo, MVT ValVT, MCRegister Reg,
MVT LocVT, LocInfo HTP, bool IsCustom = false) {
CCValAssign Ret(HTP, ValNo, ValVT, LocVT, IsCustom);
Ret.Data = Register(RegNo);
Ret.Data = Register(Reg);
return Ret;
}

static CCValAssign getCustomReg(unsigned ValNo, MVT ValVT, unsigned RegNo,
static CCValAssign getCustomReg(unsigned ValNo, MVT ValVT, MCRegister Reg,
MVT LocVT, LocInfo HTP) {
return getReg(ValNo, ValVT, RegNo, LocVT, HTP, /*IsCustom=*/true);
return getReg(ValNo, ValVT, Reg, LocVT, HTP, /*IsCustom=*/true);
}

static CCValAssign getMem(unsigned ValNo, MVT ValVT, int64_t Offset,
Expand All @@ -112,7 +112,7 @@ class CCValAssign {
return Ret;
}

void convertToReg(unsigned RegNo) { Data = Register(RegNo); }
void convertToReg(MCRegister Reg) { Data = Register(Reg); }

void convertToMem(int64_t Offset) { Data = Offset; }

Expand Down Expand Up @@ -346,7 +346,7 @@ class CCState {
/// AllocateReg - Attempt to allocate one of the specified registers. If none
/// are available, return zero. Otherwise, return the first one available,
/// marking it and any aliases as allocated.
MCPhysReg AllocateReg(ArrayRef<MCPhysReg> Regs) {
MCRegister AllocateReg(ArrayRef<MCPhysReg> Regs) {
unsigned FirstUnalloc = getFirstUnallocated(Regs);
if (FirstUnalloc == Regs.size())
return MCRegister(); // Didn't find the reg.
Expand Down
16 changes: 8 additions & 8 deletions llvm/lib/Target/ARM/ARMCallingConv.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,7 @@ static bool f64AssignAPCS(unsigned ValNo, MVT ValVT, MVT LocVT,
static const MCPhysReg RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };

// Try to get the first register.
if (unsigned Reg = State.AllocateReg(RegList))
if (MCRegister Reg = State.AllocateReg(RegList))
State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
else {
// For the 2nd half of a v2f64, do not fail.
Expand All @@ -38,7 +38,7 @@ static bool f64AssignAPCS(unsigned ValNo, MVT ValVT, MVT LocVT,
}

// Try to get the second register.
if (unsigned Reg = State.AllocateReg(RegList))
if (MCRegister Reg = State.AllocateReg(RegList))
State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
else
State.addLoc(CCValAssign::getCustomMem(
Expand Down Expand Up @@ -67,8 +67,8 @@ static bool f64AssignAAPCS(unsigned ValNo, MVT ValVT, MVT LocVT,
static const MCPhysReg ShadowRegList[] = { ARM::R0, ARM::R1 };
static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };

unsigned Reg = State.AllocateReg(HiRegList, ShadowRegList);
if (Reg == 0) {
MCRegister Reg = State.AllocateReg(HiRegList, ShadowRegList);
if (!Reg) {

// If we had R3 unallocated only, now we still must to waste it.
Reg = State.AllocateReg(GPRArgRegs);
Expand All @@ -89,7 +89,7 @@ static bool f64AssignAAPCS(unsigned ValNo, MVT ValVT, MVT LocVT,
if (HiRegList[i] == Reg)
break;

unsigned T = State.AllocateReg(LoRegList[i]);
MCRegister T = State.AllocateReg(LoRegList[i]);
(void)T;
assert(T == LoRegList[i] && "Could not allocate register");

Expand All @@ -116,8 +116,8 @@ static bool f64RetAssign(unsigned ValNo, MVT ValVT, MVT LocVT,
static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 };
static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 };

unsigned Reg = State.AllocateReg(HiRegList, LoRegList);
if (Reg == 0)
MCRegister Reg = State.AllocateReg(HiRegList, LoRegList);
if (!Reg)
return false; // we didn't handle it

unsigned i;
Expand Down Expand Up @@ -287,7 +287,7 @@ static bool CC_ARM_AAPCS_Custom_Aggregate(unsigned ValNo, MVT ValVT,
static bool CustomAssignInRegList(unsigned ValNo, MVT ValVT, MVT LocVT,
CCValAssign::LocInfo LocInfo, CCState &State,
ArrayRef<MCPhysReg> RegList) {
unsigned Reg = State.AllocateReg(RegList);
MCRegister Reg = State.AllocateReg(RegList);
if (Reg) {
State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
return true;
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/ARM/ARMISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2915,7 +2915,7 @@ void ARMTargetLowering::HandleByVal(CCState *State, unsigned &Size,
// Byval (as with any stack) slots are always at least 4 byte aligned.
Alignment = std::max(Alignment, Align(4));

unsigned Reg = State->AllocateReg(GPRArgRegs);
MCRegister Reg = State->AllocateReg(GPRArgRegs);
if (!Reg)
return;

Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -5012,7 +5012,7 @@ static bool CC_LoongArch_GHC(unsigned ValNo, MVT ValVT, MVT LocVT,
LoongArch::R23, LoongArch::R24, LoongArch::R25,
LoongArch::R26, LoongArch::R27, LoongArch::R28,
LoongArch::R29, LoongArch::R30, LoongArch::R31};
if (unsigned Reg = State.AllocateReg(GPRList)) {
if (MCRegister Reg = State.AllocateReg(GPRList)) {
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
return false;
}
Expand All @@ -5023,7 +5023,7 @@ static bool CC_LoongArch_GHC(unsigned ValNo, MVT ValVT, MVT LocVT,
// fs0,fs1,fs2,fs3
static const MCPhysReg FPR32List[] = {LoongArch::F24, LoongArch::F25,
LoongArch::F26, LoongArch::F27};
if (unsigned Reg = State.AllocateReg(FPR32List)) {
if (MCRegister Reg = State.AllocateReg(FPR32List)) {
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
return false;
}
Expand All @@ -5034,7 +5034,7 @@ static bool CC_LoongArch_GHC(unsigned ValNo, MVT ValVT, MVT LocVT,
// fs4,fs5,fs6,fs7
static const MCPhysReg FPR64List[] = {LoongArch::F28_64, LoongArch::F29_64,
LoongArch::F30_64, LoongArch::F31_64};
if (unsigned Reg = State.AllocateReg(FPR64List)) {
if (MCRegister Reg = State.AllocateReg(FPR64List)) {
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
return false;
}
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -527,15 +527,15 @@ static void AnalyzeArguments(CCState &State,

if (!UsedStack && Parts == 2 && RegsLeft == 1) {
// Special case for 32-bit register split, see EABI section 3.3.3
unsigned Reg = State.AllocateReg(RegList);
MCRegister Reg = State.AllocateReg(RegList);
State.addLoc(CCValAssign::getReg(ValNo++, ArgVT, Reg, LocVT, LocInfo));
RegsLeft -= 1;

UsedStack = true;
CC_MSP430_AssignStack(ValNo++, ArgVT, LocVT, LocInfo, ArgFlags, State);
} else if (Parts <= RegsLeft) {
for (unsigned j = 0; j < Parts; j++) {
unsigned Reg = State.AllocateReg(RegList);
MCRegister Reg = State.AllocateReg(RegList);
State.addLoc(CCValAssign::getReg(ValNo++, ArgVT, Reg, LocVT, LocInfo));
RegsLeft--;
}
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/Mips/MipsISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2991,7 +2991,7 @@ static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
} else {
Reg = State.AllocateReg(F64Regs);
// Shadow int registers
unsigned Reg2 = State.AllocateReg(IntRegs);
MCRegister Reg2 = State.AllocateReg(IntRegs);
if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
State.AllocateReg(IntRegs);
State.AllocateReg(IntRegs);
Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/Target/PowerPC/PPCCallingConv.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -151,7 +151,7 @@ static bool CC_PPC32_SPE_CustomSplitFP64(unsigned &ValNo, MVT &ValVT,
static const MCPhysReg LoRegList[] = { PPC::R4, PPC::R6, PPC::R8, PPC::R10 };

// Try to get the first register.
unsigned Reg = State.AllocateReg(HiRegList);
MCRegister Reg = State.AllocateReg(HiRegList);
if (!Reg)
return false;

Expand All @@ -160,7 +160,7 @@ static bool CC_PPC32_SPE_CustomSplitFP64(unsigned &ValNo, MVT &ValVT,
if (HiRegList[i] == Reg)
break;

unsigned T = State.AllocateReg(LoRegList[i]);
MCRegister T = State.AllocateReg(LoRegList[i]);
(void)T;
assert(T == LoRegList[i] && "Could not allocate register");

Expand All @@ -180,7 +180,7 @@ static bool CC_PPC32_SPE_RetF64(unsigned &ValNo, MVT &ValVT,
static const MCPhysReg LoRegList[] = { PPC::R4 };

// Try to get the first register.
unsigned Reg = State.AllocateReg(HiRegList, LoRegList);
MCRegister Reg = State.AllocateReg(HiRegList, LoRegList);
if (!Reg)
return false;

Expand Down
22 changes: 11 additions & 11 deletions llvm/lib/Target/PowerPC/PPCISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -6904,7 +6904,7 @@ static bool CC_AIX(unsigned ValNo, MVT ValVT, MVT LocVT,
while (NextReg != GPRs.size() &&
!isGPRShadowAligned(GPRs[NextReg], ObjAlign)) {
// Shadow allocate next registers since its aligment is not strict enough.
unsigned Reg = State.AllocateReg(GPRs);
MCRegister Reg = State.AllocateReg(GPRs);
// Allocate the stack space shadowed by said register.
State.AllocateStack(PtrSize, PtrAlign);
assert(Reg && "Alocating register unexpectedly failed.");
Expand All @@ -6915,7 +6915,7 @@ static bool CC_AIX(unsigned ValNo, MVT ValVT, MVT LocVT,
const unsigned StackSize = alignTo(ByValSize, ObjAlign);
unsigned Offset = State.AllocateStack(StackSize, ObjAlign);
for (const unsigned E = Offset + StackSize; Offset < E; Offset += PtrSize) {
if (unsigned Reg = State.AllocateReg(GPRs))
if (MCRegister Reg = State.AllocateReg(GPRs))
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, RegVT, LocInfo));
else {
State.addLoc(CCValAssign::getMem(ValNo, MVT::INVALID_SIMPLE_VALUE_TYPE,
Expand All @@ -6942,7 +6942,7 @@ static bool CC_AIX(unsigned ValNo, MVT ValVT, MVT LocVT,
if (ValVT.getFixedSizeInBits() < RegVT.getFixedSizeInBits())
LocInfo = ArgFlags.isSExt() ? CCValAssign::LocInfo::SExt
: CCValAssign::LocInfo::ZExt;
if (unsigned Reg = State.AllocateReg(GPRs))
if (MCRegister Reg = State.AllocateReg(GPRs))
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, RegVT, LocInfo));
else
State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, RegVT, LocInfo));
Expand All @@ -6957,13 +6957,13 @@ static bool CC_AIX(unsigned ValNo, MVT ValVT, MVT LocVT,
// This includes f64 in 64-bit mode for ABI compatibility.
const unsigned Offset =
State.AllocateStack(IsPPC64 ? 8 : StoreSize, Align(4));
unsigned FReg = State.AllocateReg(FPR);
MCRegister FReg = State.AllocateReg(FPR);
if (FReg)
State.addLoc(CCValAssign::getReg(ValNo, ValVT, FReg, LocVT, LocInfo));

// Reserve and initialize GPRs or initialize the PSA as required.
for (unsigned I = 0; I < StoreSize; I += PtrSize) {
if (unsigned Reg = State.AllocateReg(GPRs)) {
if (MCRegister Reg = State.AllocateReg(GPRs)) {
assert(FReg && "An FPR should be available when a GPR is reserved.");
if (State.isVarArg()) {
// Successfully reserved GPRs are only initialized for vararg calls.
Expand Down Expand Up @@ -7003,7 +7003,7 @@ static bool CC_AIX(unsigned ValNo, MVT ValVT, MVT LocVT,
if (!State.isVarArg()) {
// If there are vector registers remaining we don't consume any stack
// space.
if (unsigned VReg = State.AllocateReg(VR)) {
if (MCRegister VReg = State.AllocateReg(VR)) {
State.addLoc(CCValAssign::getReg(ValNo, ValVT, VReg, LocVT, LocInfo));
return false;
}
Expand All @@ -7021,7 +7021,7 @@ static bool CC_AIX(unsigned ValNo, MVT ValVT, MVT LocVT,
while (NextRegIndex != GPRs.size() &&
!isGPRShadowAligned(GPRs[NextRegIndex], VecAlign)) {
// Shadow allocate register and its stack shadow.
unsigned Reg = State.AllocateReg(GPRs);
MCRegister Reg = State.AllocateReg(GPRs);
State.AllocateStack(PtrSize, PtrAlign);
assert(Reg && "Allocating register unexpectedly failed.");
(void)Reg;
Expand All @@ -7033,7 +7033,7 @@ static bool CC_AIX(unsigned ValNo, MVT ValVT, MVT LocVT,
// through ellipses) and shadow GPRs (unlike arguments to non-vaarg
// functions)
if (State.isFixed(ValNo)) {
if (unsigned VReg = State.AllocateReg(VR)) {
if (MCRegister VReg = State.AllocateReg(VR)) {
State.addLoc(CCValAssign::getReg(ValNo, ValVT, VReg, LocVT, LocInfo));
// Shadow allocate GPRs and stack space even though we pass in a VR.
for (unsigned I = 0; I != VecSize; I += PtrSize)
Expand Down Expand Up @@ -7062,8 +7062,8 @@ static bool CC_AIX(unsigned ValNo, MVT ValVT, MVT LocVT,
State.addLoc(
CCValAssign::getCustomMem(ValNo, ValVT, Offset, LocVT, LocInfo));

const unsigned FirstReg = State.AllocateReg(PPC::R9);
const unsigned SecondReg = State.AllocateReg(PPC::R10);
const MCRegister FirstReg = State.AllocateReg(PPC::R9);
const MCRegister SecondReg = State.AllocateReg(PPC::R10);
assert(FirstReg && SecondReg &&
"Allocating R9 or R10 unexpectedly failed.");
State.addLoc(
Expand All @@ -7080,7 +7080,7 @@ static bool CC_AIX(unsigned ValNo, MVT ValVT, MVT LocVT,
State.addLoc(
CCValAssign::getCustomMem(ValNo, ValVT, Offset, LocVT, LocInfo));
for (unsigned I = 0; I != VecSize; I += PtrSize) {
const unsigned Reg = State.AllocateReg(GPRs);
const MCRegister Reg = State.AllocateReg(GPRs);
assert(Reg && "Failed to allocated register for vararg vector argument");
State.addLoc(
CCValAssign::getCustomReg(ValNo, ValVT, Reg, RegVT, LocInfo));
Expand Down
22 changes: 11 additions & 11 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -18625,7 +18625,7 @@ bool RISCV::CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
// Static chain parameter must not be passed in normal argument registers,
// so we assign t2 for it as done in GCC's __builtin_call_with_static_chain
if (ArgFlags.isNest()) {
if (unsigned Reg = State.AllocateReg(RISCV::X7)) {
if (MCRegister Reg = State.AllocateReg(RISCV::X7)) {
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
return false;
}
Expand Down Expand Up @@ -19098,7 +19098,7 @@ bool RISCV::CC_RISCV_FastCC(const DataLayout &DL, RISCVABI::ABI ABI,
const RISCVTargetLowering &TLI,
RVVArgDispatcher &RVVDispatcher) {
if (LocVT == MVT::i32 || LocVT == MVT::i64) {
if (unsigned Reg = State.AllocateReg(getFastCCArgGPRs(ABI))) {
if (MCRegister Reg = State.AllocateReg(getFastCCArgGPRs(ABI))) {
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
return false;
}
Expand All @@ -19113,7 +19113,7 @@ bool RISCV::CC_RISCV_FastCC(const DataLayout &DL, RISCVABI::ABI ABI,
RISCV::F15_H, RISCV::F16_H, RISCV::F17_H, RISCV::F0_H, RISCV::F1_H,
RISCV::F2_H, RISCV::F3_H, RISCV::F4_H, RISCV::F5_H, RISCV::F6_H,
RISCV::F7_H, RISCV::F28_H, RISCV::F29_H, RISCV::F30_H, RISCV::F31_H};
if (unsigned Reg = State.AllocateReg(FPR16List)) {
if (MCRegister Reg = State.AllocateReg(FPR16List)) {
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
return false;
}
Expand All @@ -19125,7 +19125,7 @@ bool RISCV::CC_RISCV_FastCC(const DataLayout &DL, RISCVABI::ABI ABI,
RISCV::F15_F, RISCV::F16_F, RISCV::F17_F, RISCV::F0_F, RISCV::F1_F,
RISCV::F2_F, RISCV::F3_F, RISCV::F4_F, RISCV::F5_F, RISCV::F6_F,
RISCV::F7_F, RISCV::F28_F, RISCV::F29_F, RISCV::F30_F, RISCV::F31_F};
if (unsigned Reg = State.AllocateReg(FPR32List)) {
if (MCRegister Reg = State.AllocateReg(FPR32List)) {
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
return false;
}
Expand All @@ -19137,7 +19137,7 @@ bool RISCV::CC_RISCV_FastCC(const DataLayout &DL, RISCVABI::ABI ABI,
RISCV::F15_D, RISCV::F16_D, RISCV::F17_D, RISCV::F0_D, RISCV::F1_D,
RISCV::F2_D, RISCV::F3_D, RISCV::F4_D, RISCV::F5_D, RISCV::F6_D,
RISCV::F7_D, RISCV::F28_D, RISCV::F29_D, RISCV::F30_D, RISCV::F31_D};
if (unsigned Reg = State.AllocateReg(FPR64List)) {
if (MCRegister Reg = State.AllocateReg(FPR64List)) {
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
return false;
}
Expand All @@ -19149,7 +19149,7 @@ bool RISCV::CC_RISCV_FastCC(const DataLayout &DL, RISCVABI::ABI ABI,
(LocVT == MVT::f32 && Subtarget.hasStdExtZfinx()) ||
(LocVT == MVT::f64 && Subtarget.is64Bit() &&
Subtarget.hasStdExtZdinx())) {
if (unsigned Reg = State.AllocateReg(getFastCCArgGPRs(ABI))) {
if (MCRegister Reg = State.AllocateReg(getFastCCArgGPRs(ABI))) {
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
return false;
}
Expand Down Expand Up @@ -19184,7 +19184,7 @@ bool RISCV::CC_RISCV_FastCC(const DataLayout &DL, RISCVABI::ABI ABI,
CCValAssign::getReg(ValNo, ValVT, AllocatedVReg, LocVT, LocInfo));
} else {
// Try and pass the address via a "fast" GPR.
if (unsigned GPRReg = State.AllocateReg(getFastCCArgGPRs(ABI))) {
if (MCRegister GPRReg = State.AllocateReg(getFastCCArgGPRs(ABI))) {
LocInfo = CCValAssign::Indirect;
LocVT = TLI.getSubtarget().getXLenVT();
State.addLoc(CCValAssign::getReg(ValNo, ValVT, GPRReg, LocVT, LocInfo));
Expand Down Expand Up @@ -19222,7 +19222,7 @@ bool RISCV::CC_RISCV_GHC(unsigned ValNo, MVT ValVT, MVT LocVT,
if (LocVT == MVT::i32 || LocVT == MVT::i64) {
// Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, R7, SpLim
// s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11
if (unsigned Reg = State.AllocateReg(GPRList)) {
if (MCRegister Reg = State.AllocateReg(GPRList)) {
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
return false;
}
Expand All @@ -19237,7 +19237,7 @@ bool RISCV::CC_RISCV_GHC(unsigned ValNo, MVT ValVT, MVT LocVT,
static const MCPhysReg FPR32List[] = {RISCV::F8_F, RISCV::F9_F,
RISCV::F18_F, RISCV::F19_F,
RISCV::F20_F, RISCV::F21_F};
if (unsigned Reg = State.AllocateReg(FPR32List)) {
if (MCRegister Reg = State.AllocateReg(FPR32List)) {
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
return false;
}
Expand All @@ -19249,7 +19249,7 @@ bool RISCV::CC_RISCV_GHC(unsigned ValNo, MVT ValVT, MVT LocVT,
static const MCPhysReg FPR64List[] = {RISCV::F22_D, RISCV::F23_D,
RISCV::F24_D, RISCV::F25_D,
RISCV::F26_D, RISCV::F27_D};
if (unsigned Reg = State.AllocateReg(FPR64List)) {
if (MCRegister Reg = State.AllocateReg(FPR64List)) {
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
return false;
}
Expand All @@ -19258,7 +19258,7 @@ bool RISCV::CC_RISCV_GHC(unsigned ValNo, MVT ValVT, MVT LocVT,
if ((LocVT == MVT::f32 && Subtarget.hasStdExtZfinx()) ||
(LocVT == MVT::f64 && Subtarget.hasStdExtZdinx() &&
Subtarget.is64Bit())) {
if (unsigned Reg = State.AllocateReg(GPRList)) {
if (MCRegister Reg = State.AllocateReg(GPRList)) {
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
return false;
}
Expand Down
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