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[NVPTX][NFC] Update tests to use bfloat type (#101493)
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Intrinsics are defined with a bfloat type as of commit
250f2bb, not i16 and i32 storage types.
As such declarations are no longer needed once the correct types are
used.
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@hdelan
hdelan authored Aug 9, 2024
1 parent 165c6d1 commit 8a5e179
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116 changes: 48 additions & 68 deletions llvm/test/CodeGen/NVPTX/math-intrins-sm80-ptx70-autoupgrade.ll
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Original file line number Diff line number Diff line change
@@ -1,56 +1,36 @@
; RUN: llc < %s -march=nvptx64 -mcpu=sm_80 -mattr=+ptx70 | FileCheck %s
; RUN: %if ptxas-11.0 %{ llc < %s -march=nvptx64 -mcpu=sm_80 -mattr=+ptx70 | %ptxas-verify -arch=sm_80 %}

declare i16 @llvm.nvvm.abs.bf16(i16)
declare i32 @llvm.nvvm.abs.bf16x2(i32)
declare i16 @llvm.nvvm.neg.bf16(i16)
declare i32 @llvm.nvvm.neg.bf16x2(i32)

declare i16 @llvm.nvvm.fmin.bf16(i16, i16)
declare i16 @llvm.nvvm.fmin.nan.bf16(i16, i16)
declare i32 @llvm.nvvm.fmin.bf16x2(i32, i32)
declare i32 @llvm.nvvm.fmin.nan.bf16x2(i32, i32)

declare i16 @llvm.nvvm.fmax.bf16(i16, i16)
declare i16 @llvm.nvvm.fmax.nan.bf16(i16, i16)
declare i32 @llvm.nvvm.fmax.bf16x2(i32, i32)
declare i32 @llvm.nvvm.fmax.nan.bf16x2(i32, i32)

declare i16 @llvm.nvvm.fma.rn.bf16(i16, i16, i16)
declare i16 @llvm.nvvm.fma.rn.relu.bf16(i16, i16, i16)
declare i32 @llvm.nvvm.fma.rn.bf16x2(i32, i32, i32)
declare i32 @llvm.nvvm.fma.rn.relu.bf16x2(i32, i32, i32)

; CHECK-LABEL: abs_bf16
define i16 @abs_bf16(i16 %0) {
define bfloat @abs_bf16(bfloat %0) {
; CHECK-NOT: call
; CHECK: abs.bf16
%res = call i16 @llvm.nvvm.abs.bf16(i16 %0);
ret i16 %res
%res = call bfloat @llvm.nvvm.abs.bf16(bfloat %0);
ret bfloat %res
}

; CHECK-LABEL: abs_bf16x2
define i32 @abs_bf16x2(i32 %0) {
define <2 x bfloat> @abs_bf16x2(<2 x bfloat> %0) {
; CHECK-NOT: call
; CHECK: abs.bf16x2
%res = call i32 @llvm.nvvm.abs.bf16x2(i32 %0);
ret i32 %res
%res = call <2 x bfloat> @llvm.nvvm.abs.bf16x2(<2 x bfloat> %0);
ret <2 x bfloat> %res
}

; CHECK-LABEL: neg_bf16
define i16 @neg_bf16(i16 %0) {
define bfloat @neg_bf16(bfloat %0) {
; CHECK-NOT: call
; CHECK: neg.bf16
%res = call i16 @llvm.nvvm.neg.bf16(i16 %0);
ret i16 %res
%res = call bfloat @llvm.nvvm.neg.bf16(bfloat %0);
ret bfloat %res
}

; CHECK-LABEL: neg_bf16x2
define i32 @neg_bf16x2(i32 %0) {
define <2 x bfloat> @neg_bf16x2(<2 x bfloat> %0) {
; CHECK-NOT: call
; CHECK: neg.bf16x2
%res = call i32 @llvm.nvvm.neg.bf16x2(i32 %0);
ret i32 %res
%res = call <2 x bfloat> @llvm.nvvm.neg.bf16x2(<2 x bfloat> %0);
ret <2 x bfloat> %res
}

; CHECK-LABEL: fmin_nan_f
Expand Down Expand Up @@ -134,35 +114,35 @@ define <2 x half> @fmin_ftz_nan_f16x2(<2 x half> %0, <2 x half> %1) {
}

; CHECK-LABEL: fmin_bf16
define i16 @fmin_bf16(i16 %0, i16 %1) {
define bfloat @fmin_bf16(bfloat %0, bfloat %1) {
; CHECK-NOT: call
; CHECK: min.bf16
%res = call i16 @llvm.nvvm.fmin.bf16(i16 %0, i16 %1)
ret i16 %res
%res = call bfloat @llvm.nvvm.fmin.bf16(bfloat %0, bfloat %1)
ret bfloat %res
}

; CHECK-LABEL: fmin_nan_bf16
define i16 @fmin_nan_bf16(i16 %0, i16 %1) {
define bfloat @fmin_nan_bf16(bfloat %0, bfloat %1) {
; CHECK-NOT: call
; CHECK: min.NaN.bf16
%res = call i16 @llvm.nvvm.fmin.nan.bf16(i16 %0, i16 %1)
ret i16 %res
%res = call bfloat @llvm.nvvm.fmin.nan.bf16(bfloat %0, bfloat %1)
ret bfloat %res
}

; CHECK-LABEL: fmin_bf16x2
define i32 @fmin_bf16x2(i32 %0, i32 %1) {
define <2 x bfloat> @fmin_bf16x2(<2 x bfloat> %0, <2 x bfloat> %1) {
; CHECK-NOT: call
; CHECK: min.bf16x2
%res = call i32 @llvm.nvvm.fmin.bf16x2(i32 %0, i32 %1)
ret i32 %res
%res = call <2 x bfloat> @llvm.nvvm.fmin.bf16x2(<2 x bfloat> %0, <2 x bfloat> %1)
ret <2 x bfloat> %res
}

; CHECK-LABEL: fmin_nan_bf16x2
define i32 @fmin_nan_bf16x2(i32 %0, i32 %1) {
define <2 x bfloat> @fmin_nan_bf16x2(<2 x bfloat> %0, <2 x bfloat> %1) {
; CHECK-NOT: call
; CHECK: min.NaN.bf16x2
%res = call i32 @llvm.nvvm.fmin.nan.bf16x2(i32 %0, i32 %1)
ret i32 %res
%res = call <2 x bfloat> @llvm.nvvm.fmin.nan.bf16x2(<2 x bfloat> %0, <2 x bfloat> %1)
ret <2 x bfloat> %res
}

; CHECK-LABEL: fmax_nan_f
Expand Down Expand Up @@ -246,35 +226,35 @@ define <2 x half> @fmax_ftz_nan_f16x2(<2 x half> %0, <2 x half> %1) {
}

; CHECK-LABEL: fmax_bf16
define i16 @fmax_bf16(i16 %0, i16 %1) {
define bfloat @fmax_bf16(bfloat %0, bfloat %1) {
; CHECK-NOT: call
; CHECK: max.bf16
%res = call i16 @llvm.nvvm.fmax.bf16(i16 %0, i16 %1)
ret i16 %res
%res = call bfloat @llvm.nvvm.fmax.bf16(bfloat %0, bfloat %1)
ret bfloat %res
}

; CHECK-LABEL: fmax_nan_bf16
define i16 @fmax_nan_bf16(i16 %0, i16 %1) {
define bfloat @fmax_nan_bf16(bfloat %0, bfloat %1) {
; CHECK-NOT: call
; CHECK: max.NaN.bf16
%res = call i16 @llvm.nvvm.fmax.nan.bf16(i16 %0, i16 %1)
ret i16 %res
%res = call bfloat @llvm.nvvm.fmax.nan.bf16(bfloat %0, bfloat %1)
ret bfloat %res
}

; CHECK-LABEL: fmax_bf16x2
define i32 @fmax_bf16x2(i32 %0, i32 %1) {
define <2 x bfloat> @fmax_bf16x2(<2 x bfloat> %0, <2 x bfloat> %1) {
; CHECK-NOT: call
; CHECK: max.bf16x2
%res = call i32 @llvm.nvvm.fmax.bf16x2(i32 %0, i32 %1)
ret i32 %res
%res = call <2 x bfloat> @llvm.nvvm.fmax.bf16x2(<2 x bfloat> %0, <2 x bfloat> %1)
ret <2 x bfloat> %res
}

; CHECK-LABEL: fmax_nan_bf16x2
define i32 @fmax_nan_bf16x2(i32 %0, i32 %1) {
define <2 x bfloat> @fmax_nan_bf16x2(<2 x bfloat> %0, <2 x bfloat> %1) {
; CHECK-NOT: call
; CHECK: max.NaN.bf16x2
%res = call i32 @llvm.nvvm.fmax.nan.bf16x2(i32 %0, i32 %1)
ret i32 %res
%res = call <2 x bfloat> @llvm.nvvm.fmax.nan.bf16x2(<2 x bfloat> %0, <2 x bfloat> %1)
ret <2 x bfloat> %res
}

; CHECK-LABEL: fma_rn_relu_f16
Expand Down Expand Up @@ -310,33 +290,33 @@ define <2 x half> @fma_rn_ftz_relu_f16x2(<2 x half> %0, <2 x half> %1, <2 x half
}

; CHECK-LABEL: fma_rn_bf16
define i16 @fma_rn_bf16(i16 %0, i16 %1, i16 %2) {
define bfloat @fma_rn_bf16(bfloat %0, bfloat %1, bfloat %2) {
; CHECK-NOT: call
; CHECK: fma.rn.bf16
%res = call i16 @llvm.nvvm.fma.rn.bf16(i16 %0, i16 %1, i16 %2)
ret i16 %res
%res = call bfloat @llvm.nvvm.fma.rn.bf16(bfloat %0, bfloat %1, bfloat %2)
ret bfloat %res
}

; CHECK-LABEL: fma_rn_relu_bf16
define i16 @fma_rn_relu_bf16(i16 %0, i16 %1, i16 %2) {
define bfloat @fma_rn_relu_bf16(bfloat %0, bfloat %1, bfloat %2) {
; CHECK-NOT: call
; CHECK: fma.rn.relu.bf16
%res = call i16 @llvm.nvvm.fma.rn.relu.bf16(i16 %0, i16 %1, i16 %2)
ret i16 %res
%res = call bfloat @llvm.nvvm.fma.rn.relu.bf16(bfloat %0, bfloat %1, bfloat %2)
ret bfloat %res
}

; CHECK-LABEL: fma_rn_bf16x2
define i32 @fma_rn_bf16x2(i32 %0, i32 %1, i32 %2) {
define <2 x bfloat> @fma_rn_bf16x2(<2 x bfloat> %0, <2 x bfloat> %1, <2 x bfloat> %2) {
; CHECK-NOT: call
; CHECK: fma.rn.bf16x2
%res = call i32 @llvm.nvvm.fma.rn.bf16x2(i32 %0, i32 %1, i32 %2)
ret i32 %res
%res = call <2 x bfloat> @llvm.nvvm.fma.rn.bf16x2(<2 x bfloat> %0, <2 x bfloat> %1, <2 x bfloat> %2)
ret <2 x bfloat> %res
}

; CHECK-LABEL: fma_rn_relu_bf16x2
define i32 @fma_rn_relu_bf16x2(i32 %0, i32 %1, i32 %2) {
define <2 x bfloat> @fma_rn_relu_bf16x2(<2 x bfloat> %0, <2 x bfloat> %1, <2 x bfloat> %2) {
; CHECK-NOT: call
; CHECK: fma.rn.relu.bf16x2
%res = call i32 @llvm.nvvm.fma.rn.relu.bf16x2(i32 %0, i32 %1, i32 %2)
ret i32 %res
%res = call <2 x bfloat> @llvm.nvvm.fma.rn.relu.bf16x2(<2 x bfloat> %0, <2 x bfloat> %1, <2 x bfloat> %2)
ret <2 x bfloat> %res
}
82 changes: 24 additions & 58 deletions llvm/test/CodeGen/NVPTX/math-intrins-sm86-ptx72-autoupgrade.ll
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Original file line number Diff line number Diff line change
@@ -1,40 +1,6 @@
; RUN: llc < %s -march=nvptx64 -mcpu=sm_86 -mattr=+ptx72 | FileCheck %s
; RUN: %if ptxas-11.2 %{ llc < %s -march=nvptx64 -mcpu=sm_86 -mattr=+ptx72 | %ptxas-verify -arch=sm_86 %}

declare half @llvm.nvvm.fmin.xorsign.abs.f16(half, half)
declare half @llvm.nvvm.fmin.ftz.xorsign.abs.f16(half, half)
declare half @llvm.nvvm.fmin.nan.xorsign.abs.f16(half, half)
declare half @llvm.nvvm.fmin.ftz.nan.xorsign.abs.f16(half, half)
declare <2 x half> @llvm.nvvm.fmin.xorsign.abs.f16x2(<2 x half> , <2 x half>)
declare <2 x half> @llvm.nvvm.fmin.ftz.xorsign.abs.f16x2(<2 x half> , <2 x half>)
declare <2 x half> @llvm.nvvm.fmin.nan.xorsign.abs.f16x2(<2 x half> , <2 x half>)
declare <2 x half> @llvm.nvvm.fmin.ftz.nan.xorsign.abs.f16x2(<2 x half> , <2 x half>)
declare i16 @llvm.nvvm.fmin.xorsign.abs.bf16(i16, i16)
declare i16 @llvm.nvvm.fmin.nan.xorsign.abs.bf16(i16, i16)
declare i32 @llvm.nvvm.fmin.xorsign.abs.bf16x2(i32, i32)
declare i32 @llvm.nvvm.fmin.nan.xorsign.abs.bf16x2(i32, i32)
declare float @llvm.nvvm.fmin.xorsign.abs.f(float, float)
declare float @llvm.nvvm.fmin.ftz.xorsign.abs.f(float, float)
declare float @llvm.nvvm.fmin.nan.xorsign.abs.f(float, float)
declare float @llvm.nvvm.fmin.ftz.nan.xorsign.abs.f(float, float)

declare half @llvm.nvvm.fmax.xorsign.abs.f16(half, half)
declare half @llvm.nvvm.fmax.ftz.xorsign.abs.f16(half, half)
declare half @llvm.nvvm.fmax.nan.xorsign.abs.f16(half, half)
declare half @llvm.nvvm.fmax.ftz.nan.xorsign.abs.f16(half, half)
declare <2 x half> @llvm.nvvm.fmax.xorsign.abs.f16x2(<2 x half> , <2 x half>)
declare <2 x half> @llvm.nvvm.fmax.ftz.xorsign.abs.f16x2(<2 x half> , <2 x half>)
declare <2 x half> @llvm.nvvm.fmax.nan.xorsign.abs.f16x2(<2 x half> , <2 x half>)
declare <2 x half> @llvm.nvvm.fmax.ftz.nan.xorsign.abs.f16x2(<2 x half> , <2 x half>)
declare i16 @llvm.nvvm.fmax.xorsign.abs.bf16(i16, i16)
declare i16 @llvm.nvvm.fmax.nan.xorsign.abs.bf16(i16, i16)
declare i32 @llvm.nvvm.fmax.xorsign.abs.bf16x2(i32, i32)
declare i32 @llvm.nvvm.fmax.nan.xorsign.abs.bf16x2(i32, i32)
declare float @llvm.nvvm.fmax.xorsign.abs.f(float, float)
declare float @llvm.nvvm.fmax.ftz.xorsign.abs.f(float, float)
declare float @llvm.nvvm.fmax.nan.xorsign.abs.f(float, float)
declare float @llvm.nvvm.fmax.ftz.nan.xorsign.abs.f(float, float)

; CHECK-LABEL: fmin_xorsign_abs_f16
define half @fmin_xorsign_abs_f16(half %0, half %1) {
; CHECK-NOT: call
Expand Down Expand Up @@ -100,35 +66,35 @@ define <2 x half> @fmin_ftz_nan_xorsign_abs_f16x2(<2 x half> %0, <2 x half> %1)
}

; CHECK-LABEL: fmin_xorsign_abs_bf16
define i16 @fmin_xorsign_abs_bf16(i16 %0, i16 %1) {
define bfloat @fmin_xorsign_abs_bf16(bfloat %0, bfloat %1) {
; CHECK-NOT: call
; CHECK: min.xorsign.abs.bf16
%res = call i16 @llvm.nvvm.fmin.xorsign.abs.bf16(i16 %0, i16 %1)
ret i16 %res
%res = call bfloat @llvm.nvvm.fmin.xorsign.abs.bf16(bfloat %0, bfloat %1)
ret bfloat %res
}

; CHECK-LABEL: fmin_nan_xorsign_abs_bf16
define i16 @fmin_nan_xorsign_abs_bf16(i16 %0, i16 %1) {
define bfloat @fmin_nan_xorsign_abs_bf16(bfloat %0, bfloat %1) {
; CHECK-NOT: call
; CHECK: min.NaN.xorsign.abs.bf16
%res = call i16 @llvm.nvvm.fmin.nan.xorsign.abs.bf16(i16 %0, i16 %1)
ret i16 %res
%res = call bfloat @llvm.nvvm.fmin.nan.xorsign.abs.bf16(bfloat %0, bfloat %1)
ret bfloat %res
}

; CHECK-LABEL: fmin_xorsign_abs_bf16x2
define i32 @fmin_xorsign_abs_bf16x2(i32 %0, i32 %1) {
define <2 x bfloat> @fmin_xorsign_abs_bf16x2(<2 x bfloat> %0, <2 x bfloat> %1) {
; CHECK-NOT: call
; CHECK: min.xorsign.abs.bf16x2
%res = call i32 @llvm.nvvm.fmin.xorsign.abs.bf16x2(i32 %0, i32 %1)
ret i32 %res
%res = call <2 x bfloat> @llvm.nvvm.fmin.xorsign.abs.bf16x2(<2 x bfloat> %0, <2 x bfloat> %1)
ret <2 x bfloat> %res
}

; CHECK-LABEL: fmin_nan_xorsign_abs_bf16x2
define i32 @fmin_nan_xorsign_abs_bf16x2(i32 %0, i32 %1) {
define <2 x bfloat> @fmin_nan_xorsign_abs_bf16x2(<2 x bfloat> %0, <2 x bfloat> %1) {
; CHECK-NOT: call
; CHECK: min.NaN.xorsign.abs.bf16x2
%res = call i32 @llvm.nvvm.fmin.nan.xorsign.abs.bf16x2(i32 %0, i32 %1)
ret i32 %res
%res = call <2 x bfloat> @llvm.nvvm.fmin.nan.xorsign.abs.bf16x2(<2 x bfloat> %0, <2 x bfloat> %1)
ret <2 x bfloat> %res
}

; CHECK-LABEL: fmin_xorsign_abs_f
Expand Down Expand Up @@ -228,35 +194,35 @@ define <2 x half> @fmax_ftz_nan_xorsign_abs_f16x2(<2 x half> %0, <2 x half> %1)
}

; CHECK-LABEL: fmax_xorsign_abs_bf16
define i16 @fmax_xorsign_abs_bf16(i16 %0, i16 %1) {
define bfloat @fmax_xorsign_abs_bf16(bfloat %0, bfloat %1) {
; CHECK-NOT: call
; CHECK: max.xorsign.abs.bf16
%res = call i16 @llvm.nvvm.fmax.xorsign.abs.bf16(i16 %0, i16 %1)
ret i16 %res
%res = call bfloat @llvm.nvvm.fmax.xorsign.abs.bf16(bfloat %0, bfloat %1)
ret bfloat %res
}

; CHECK-LABEL: fmax_nan_xorsign_abs_bf16
define i16 @fmax_nan_xorsign_abs_bf16(i16 %0, i16 %1) {
define bfloat @fmax_nan_xorsign_abs_bf16(bfloat %0, bfloat %1) {
; CHECK-NOT: call
; CHECK: max.NaN.xorsign.abs.bf16
%res = call i16 @llvm.nvvm.fmax.nan.xorsign.abs.bf16(i16 %0, i16 %1)
ret i16 %res
%res = call bfloat @llvm.nvvm.fmax.nan.xorsign.abs.bf16(bfloat %0, bfloat %1)
ret bfloat %res
}

; CHECK-LABEL: fmax_xorsign_abs_bf16x2
define i32 @fmax_xorsign_abs_bf16x2(i32 %0, i32 %1) {
define <2 x bfloat> @fmax_xorsign_abs_bf16x2(<2 x bfloat> %0, <2 x bfloat> %1) {
; CHECK-NOT: call
; CHECK: max.xorsign.abs.bf16x2
%res = call i32 @llvm.nvvm.fmax.xorsign.abs.bf16x2(i32 %0, i32 %1)
ret i32 %res
%res = call <2 x bfloat> @llvm.nvvm.fmax.xorsign.abs.bf16x2(<2 x bfloat> %0, <2 x bfloat> %1)
ret <2 x bfloat> %res
}

; CHECK-LABEL: fmax_nan_xorsign_abs_bf16x2
define i32 @fmax_nan_xorsign_abs_bf16x2(i32 %0, i32 %1) {
define <2 x bfloat> @fmax_nan_xorsign_abs_bf16x2(<2 x bfloat> %0, <2 x bfloat> %1) {
; CHECK-NOT: call
; CHECK: max.NaN.xorsign.abs.bf16x2
%res = call i32 @llvm.nvvm.fmax.nan.xorsign.abs.bf16x2(i32 %0, i32 %1)
ret i32 %res
%res = call <2 x bfloat> @llvm.nvvm.fmax.nan.xorsign.abs.bf16x2(<2 x bfloat> %0, <2 x bfloat> %1)
ret <2 x bfloat> %res
}

; CHECK-LABEL: fmax_xorsign_abs_f
Expand Down

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