Update option and option desc

llvm · May 21, 2024 · 918f004 · 918f004
1 parent a74ee80
commit 918f004
Showing 1 changed file with 3 additions and 2 deletions.
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -97,8 +97,9 @@ static cl::opt<bool> EnableMISchedLoadClustering(
     cl::init(false));
 
 static cl::opt<bool> EnableVSETVLIAfterRVVRegAlloc(
-    "riscv-vsetvli-after-rvv-regalloc", cl::Hidden,
-    cl::desc("vsetvl insertion after rvv regalloc"), cl::init(true));
+    "riscv-vsetvl-after-rvv-regalloc", cl::Hidden,
+    cl::desc("Insert vsetvls after vector register allocation"),
+    cl::init(true));
 
 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
   RegisterTargetMachine<RISCVTargetMachine> X(getTheRISCV32Target());