Fixing miscompilation

llvm · Aug 6, 2024 · e778cea · e778cea
1 parent ab11ff0
commit e778cea
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Showing 2 changed files with 6 additions and 1 deletion.
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
@@ -1740,9 +1740,13 @@ Value *InstCombinerImpl::SimplifyDemandedVectorElts(Value *V,
         Constant *CElt = CV->getAggregateElement(i);
         if (isa<ConstantExpr>(CElt))
           continue;
+
         // TODO: If a select condition element is undef, we can demand from
         // either side. If one side is known undef, choosing that side would
         // propagate undef.
+        if (isa<UndefValue>(CElt))
+          continue;
+
         if (CElt->isNullValue())
           DemandedLHS.clearBit(i);
         else

diff --git a/llvm/test/Transforms/InstCombine/pr98435.ll b/llvm/test/Transforms/InstCombine/pr98435.ll
@@ -4,7 +4,8 @@
 define <2 x i1> @pr98435(<2 x i1> %val0) {
 ; CHECK-LABEL: define <2 x i1> @pr98435(
 ; CHECK-SAME: <2 x i1> [[VAL0:%.*]]) {
-; CHECK-NEXT:    ret <2 x i1> <i1 poison, i1 true>
+; CHECK-NEXT:    [[VAL3:%.*]] = select <2 x i1> <i1 undef, i1 true>, <2 x i1> <i1 true, i1 true>, <2 x i1> [[VAL0]]
+; CHECK-NEXT:    ret <2 x i1> [[VAL3]]
 ;
   %val3 = select <2 x i1> <i1 undef, i1 true>, <2 x i1> <i1 true, i1 true>, <2 x i1> %val0
   ret <2 x i1> %val3