-
Notifications
You must be signed in to change notification settings - Fork 12.3k
Commit
This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository.
SROA: Enhance speculateSelectInstLoads
Allow the folding even if there is an intervening bitcast. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D106667
- Loading branch information
Showing
3 changed files
with
66 additions
and
17 deletions.
There are no files selected for viewing
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,35 @@ | ||
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py | ||
; RUN: opt -S -sroa < %s | FileCheck %s | ||
|
||
%st.half = type { half } | ||
|
||
; Allow speculateSelectInstLoads to fold load and select | ||
; even if there is an intervening bitcast. | ||
define <2 x i16> @test_load_bitcast_select(i1 %cond1, i1 %cond2) { | ||
; CHECK-LABEL: @test_load_bitcast_select( | ||
; CHECK-NEXT: [[TMP1:%.*]] = bitcast half 0xHFFFF to i16 | ||
; CHECK-NEXT: [[TMP2:%.*]] = bitcast half 0xH0000 to i16 | ||
; CHECK-NEXT: [[LD1_SROA_SPECULATED:%.*]] = select i1 [[COND1:%.*]], i16 [[TMP1]], i16 [[TMP2]] | ||
; CHECK-NEXT: [[V1:%.*]] = insertelement <2 x i16> undef, i16 [[LD1_SROA_SPECULATED]], i32 0 | ||
; CHECK-NEXT: [[TMP3:%.*]] = bitcast half 0xHFFFF to i16 | ||
; CHECK-NEXT: [[TMP4:%.*]] = bitcast half 0xH0000 to i16 | ||
; CHECK-NEXT: [[LD2_SROA_SPECULATED:%.*]] = select i1 [[COND2:%.*]], i16 [[TMP3]], i16 [[TMP4]] | ||
; CHECK-NEXT: [[V2:%.*]] = insertelement <2 x i16> [[V1]], i16 [[LD2_SROA_SPECULATED]], i32 1 | ||
; CHECK-NEXT: ret <2 x i16> [[V2]] | ||
; | ||
%true = alloca half, align 2 | ||
%false = alloca half, align 2 | ||
store half 0xHFFFF, half* %true, align 2 | ||
store half 0xH0000, half* %false, align 2 | ||
%false.cast = bitcast half* %false to %st.half* | ||
%true.cast = bitcast half* %true to %st.half* | ||
%sel1 = select i1 %cond1, %st.half* %true.cast, %st.half* %false.cast | ||
%cast1 = bitcast %st.half* %sel1 to i16* | ||
%ld1 = load i16, i16* %cast1, align 2 | ||
%v1 = insertelement <2 x i16> undef, i16 %ld1, i32 0 | ||
%sel2 = select i1 %cond2, %st.half* %true.cast, %st.half* %false.cast | ||
%cast2 = bitcast %st.half* %sel2 to i16* | ||
%ld2 = load i16, i16* %cast2, align 2 | ||
%v2 = insertelement <2 x i16> %v1, i16 %ld2, i32 1 | ||
ret <2 x i16> %v2 | ||
} |