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[RISCV] Miscompilation of inline assembly #100779

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shkoo opened this issue Jul 26, 2024 · 3 comments · Fixed by #100790
Closed

[RISCV] Miscompilation of inline assembly #100779

shkoo opened this issue Jul 26, 2024 · 3 comments · Fixed by #100790

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@shkoo
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shkoo commented Jul 26, 2024

It looks like LLC is miscompiling passing a register load to inline assembly:

target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32"

@_ZN5repro9MY_BUFFER17hb0f674501d5980a6E = external global <{ [16 x i8] }>

define void @using_inout() {
start:
  %0 = tail call ptr asm sideeffect alignstack "ecall", "=&{x10},0,~{vtype},~{vl},~{vxsat},~{vxrm},~{memory}"(ptr @_ZN5repro9MY_BUFFER17hb0f674501d5980a6E)
  ret void
}

Running llc on this crashes with assertions enabled (https://godbolt.org/z/1zWaoxKKE).

Without assertions, it generates incorrect code (https://godbolt.org/z/43c4W44nY); notice that it silently discards the load of the low bits of _ZN5repro9MY_BUFFER17hb0f674501d5980a6E causing an incorrect value to be loaded in register a0:

using_inout:                            # @using_inout
        lui     a0, %hi(_ZN5repro9MY_BUFFER17hb0f674501d5980a6E)
        ecall
        ret

This regression looks like it happened somewhere between llvm 17 (https://godbolt.org/z/o6eWGx68o) and llvm 18 (https://godbolt.org/z/fMMd9Gf3W).

For more background, see rust-lang/rust#128212

@llvmbot
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llvmbot commented Jul 26, 2024

@llvm/issue-subscribers-backend-risc-v

Author: None (shkoo)

It looks like LLC is miscompiling passing a register load to inline assembly:
target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
target triple = "riscv32"

@<!-- -->_ZN5repro9MY_BUFFER17hb0f674501d5980a6E = external global &lt;{ [16 x i8] }&gt;

define void @<!-- -->using_inout() {
start:
  %0 = tail call ptr asm sideeffect alignstack "ecall", "=&amp;{x10},0,~{vtype},~{vl},~{vxsat},~{vxrm},~{memory}"(ptr @<!-- -->_ZN5repro9MY_BUFFER17hb0f674501d5980a6E)
  ret void
}

Running llc on this crashes with assertions enabled (https://godbolt.org/z/1zWaoxKKE).

Without assertions, it generates incorrect code (https://godbolt.org/z/43c4W44nY); notice that it silently discards the load of the low bits of _ZN5repro9MY_BUFFER17hb0f674501d5980a6E causing an incorrect value to be loaded in register a0:

using_inout:                            # @<!-- -->using_inout
        lui     a0, %hi(_ZN5repro9MY_BUFFER17hb0f674501d5980a6E)
        ecall
        ret

This regression looks like it happened somewhere between llvm 17 (https://godbolt.org/z/o6eWGx68o) and llvm 18 (https://godbolt.org/z/fMMd9Gf3W).

For more background, see rust-lang/rust#128212

@topperc topperc self-assigned this Jul 26, 2024
topperc added a commit to topperc/llvm-project that referenced this issue Jul 26, 2024
…s register in a non-memory constraint.

If the register is used by a non-memory constraint we should disable
the fold. Otherwise, we may leave CommonOffset unassigned.

Fixes llvm#100779.
@topperc topperc added this to the LLVM 19.X Release milestone Jul 27, 2024
@github-project-automation github-project-automation bot moved this to Needs Triage in LLVM Release Status Jul 27, 2024
@topperc
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topperc commented Jul 27, 2024

/cherry-pick c901b73

llvmbot pushed a commit to llvmbot/llvm-project that referenced this issue Jul 27, 2024
…s register in a non-memory constraint. (llvm#100790)

If the register is used by a non-memory constraint we should disable the
fold. Otherwise, we may leave CommonOffset unassigned.

Fixes llvm#100779.

(cherry picked from commit c901b73)
@llvmbot
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llvmbot commented Jul 27, 2024

/pull-request #100843

tru pushed a commit to llvmbot/llvm-project that referenced this issue Jul 27, 2024
…s register in a non-memory constraint. (llvm#100790)

If the register is used by a non-memory constraint we should disable the
fold. Otherwise, we may leave CommonOffset unassigned.

Fixes llvm#100779.

(cherry picked from commit c901b73)
@tru tru moved this from Needs Triage to Done in LLVM Release Status Jul 29, 2024
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