[SLP] SLP Vectorizer miscompile from reducing abs bitwidth

[danilaml]

Bisected miscompile to this change 4a1c53f

Reduced internal test to this example:
https://godbolt.org/z/njWYP9exd

define dso_local noundef i32 @test(i32 %n) local_unnamed_addr #0 {
entry:
  %n1 = add i32 %n, 1
  %zn1 = zext nneg i32 %n1 to i64
  %m1 = mul nuw nsw i64 %zn1, 273837369
  %a1 = call noundef i64 @llvm.abs.i64(i64 %m1, i1 true)
  %t1 = trunc i64 %a1 to i32
  %n2 = add i32 %n, 2
  %zn2 = zext nneg i32 %n2 to i64
  %m2 = mul nuw nsw i64 %zn2, 273837369
  %a2 = call noundef i64 @llvm.abs.i64(i64 %m2, i1 true)
  %t2 = trunc i64 %a2 to i32

  %res1 = add i32 %t1, %t2
  ret i32 %res1
}

Running slp vectorizer on it gives

define dso_local noundef i32 @test(i32 %n) local_unnamed_addr {
  %0 = insertelement <2 x i32> poison, i32 %n, i32 0
  %1 = shufflevector <2 x i32> %0, <2 x i32> poison, <2 x i32> zeroinitializer
  %2 = add <2 x i32> %1, <i32 1, i32 2>
  %3 = mul <2 x i32> %2, <i32 273837369, i32 273837369>
  %4 = call <2 x i32> @llvm.abs.v2i32(<2 x i32> %3, i1 false)
  %5 = extractelement <2 x i32> %4, i32 0
  %6 = extractelement <2 x i32> %4, i32 1
  %res1 = add i32 %5, %6
  ret i32 %res1
}

which is incorrect. Counterexample by alive2:
https://alive2.llvm.org/ce/z/cEcY-u

[AZero13]

Do we plan on backporting this to 19.x @alexey-bataev

[alexey-bataev]

/cherry-pick 709abac

[llvmbot]

Failed to cherry-pick: 709abac

https://github.com/llvm/llvm-project/actions/runs/11419324038

Please manually backport the fix and push it to your github fork. Once this is done, please create a pull request

[alexey-bataev]

/cherry-pick 825f9cb 709abac

[llvmbot]

/pull-request #113146