[RISCV] isel generates invalid SLRIW instruction on riscv32

[shkoo]

The following crashes llc when assertions are enabled. (When they aren't, I just get invalid machine code causing an illegal instruction when executing the resultant code):

; ModuleID = 'bugpoint-reduced-simplified.bc'
source_filename = "reduced.ll"
target triple = "riscv32"

define i24 @aext(i32 %0) {
  %2 = and i32 %0, -256
  %3 = lshr exact i32 %2, 8
  %4 = trunc i32 %3 to i24
  ret i24 %4
}

Here's what I get when executing:

$ llc bugpoint-reduced-simplified.ll
LLVM ERROR: Attempting to emit SRLIW instruction but the Feature_IsRV64 predicate(s) are not met
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace.
Stack dump:
0.      Program arguments: llc bugpoint-reduced-simplified.ll
1.      Running pass 'Function Pass Manager' on module 'bugpoint-reduced-simplified.ll'.
2.      Running pass 'RISC-V Assembly Printer' on function '@aext'
 #0 0x000000000290cd5d llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) llvm/lib/Support/Unix/Signals.inc:723:11
 #1 0x000000000290d24b PrintStackTraceSignalHandler(void*) llvm/lib/Support/Unix/Signals.inc:798:1
 #2 0x000000000290b2b6 llvm::sys::RunSignalHandlers() llvm/lib/Support/Signals.cpp:105:5
 #3 0x000000000290da25 SignalHandler(int) llvm/lib/Support/Unix/Signals.inc:413:1
 #4 0x00007ffbd0a7a420 __restore_rt (/lib/x86_64-linux-gnu/libpthread.so.0+0x14420)
 #5 0x00007ffbd050d00b raise /build/glibc-SzIz7B/glibc-2.31/signal/../sysdeps/unix/sysv/linux/raise.c:51:1
 #6 0x00007ffbd04ec859 abort /build/glibc-SzIz7B/glibc-2.31/stdlib/abort.c:81:7
 #7 0x0000000002844064 llvm::report_fatal_error(llvm::Twine const&, bool) llvm/lib/Support/ErrorHandling.cpp:125:5
 #8 0x0000000002843ed2 llvm/lib/Support/ErrorHandling.cpp:83:3
 #9 0x0000000000eac075 llvm::RISCV_MC::verifyInstructionPredicates(unsigned int, llvm::FeatureBitset const&) build/lib/Target/RISCV/RISCVGenInstrInfo.inc:112254:1
#10 0x0000000000c69c4f (anonymous namespace)::RISCVAsmPrinter::emitInstruction(llvm::MachineInstr const*) llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp:228:3
#11 0x000000000126d58f llvm::AsmPrinter::emitFunctionBody() llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp:1735:13
#12 0x0000000000c69a72 (anonymous namespace)::RISCVAsmPrinter::runOnMachineFunction(llvm::MachineFunction&) llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp:376:7
#13 0x00000000016c14fc llvm::MachineFunctionPass::runOnFunction(llvm::Function&) llvm/lib/CodeGen/MachineFunctionPass.cpp:93:8
#14 0x0000000001eb850a llvm::FPPassManager::runOnFunction(llvm::Function&) llvm/lib/IR/LegacyPassManager.cpp:1435:23
#15 0x0000000001ebd332 llvm::FPPassManager::runOnModule(llvm::Module&) llvm/lib/IR/LegacyPassManager.cpp:1481:16
#16 0x0000000001eb8dbb (anonymous namespace)::MPPassManager::runOnModule(llvm::Module&) llvm/lib/IR/LegacyPassManager.cpp:1550:23
#17 0x0000000001eb893d llvm::legacy::PassManagerImpl::run(llvm::Module&) llvm/lib/IR/LegacyPassManager.cpp:535:16
#18 0x0000000001ebd611 llvm::legacy::PassManager::run(llvm::Module&) llvm/lib/IR/LegacyPassManager.cpp:1677:3
#19 0x0000000000c19c11 compileModule(char**, llvm::LLVMContext&) llvm/tools/llc/llc.cpp:743:41
#20 0x0000000000c17f2d main llvm/tools/llc/llc.cpp:416:13
#21 0x00007ffbd04ee083 __libc_start_main /build/glibc-SzIz7B/glibc-2.31/csu/../csu/libc-start.c:342:3
#22 0x0000000000c1770e _start (build/bin/llc+0xc1770e)
Aborted (core dumped)

I'm building from commit ID beffc82:

LLVM (http://llvm.org/):
  LLVM version 18.0.0git
  DEBUG build with assertions.
  Default target: 
  Host CPU: znver2

  Registered Targets:
    riscv32 - 32-bit RISC-V
    riscv64 - 64-bit RISC-V

[llvmbot]

@llvm/issue-subscribers-backend-risc-v

Author: None (shkoo)

The following crashes llc when assertions are enabled. (When they aren't, I just get invalid machine code causing an illegal instruction when executing the resultant code): ``` ; ModuleID = 'bugpoint-reduced-simplified.bc' source_filename = "reduced.ll" target triple = "riscv32"

define i24 @aext(i32 %0) {
%2 = and i32 %0, -256
%3 = lshr exact i32 %2, 8
%4 = trunc i32 %3 to i24
ret i24 %4
}

Here's what I get when executing:

$ llc bugpoint-reduced-simplified.ll
LLVM ERROR: Attempting to emit SRLIW instruction but the Feature_IsRV64 predicate(s) are not met
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace.
Stack dump:
0. Program arguments: llc bugpoint-reduced-simplified.ll

1.  Running pass 'Function Pass Manager' on module 'bugpoint-reduced-simplified.ll'.
   

2.  Running pass 'RISC-V Assembly Printer' on function '@<!-- -->aext'
   

#0 0x000000000290cd5d llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) llvm/lib/Support/Unix/Signals.inc:723:11
#1 0x000000000290d24b PrintStackTraceSignalHandler(void*) llvm/lib/Support/Unix/Signals.inc:798:1
#2 0x000000000290b2b6 llvm::sys::RunSignalHandlers() llvm/lib/Support/Signals.cpp:105:5
#3 0x000000000290da25 SignalHandler(int) llvm/lib/Support/Unix/Signals.inc:413:1
#4 0x00007ffbd0a7a420 __restore_rt (/lib/x86_64-linux-gnu/libpthread.so.0+0x14420)
#5 0x00007ffbd050d00b raise /build/glibc-SzIz7B/glibc-2.31/signal/../sysdeps/unix/sysv/linux/raise.c:51:1
#6 0x00007ffbd04ec859 abort /build/glibc-SzIz7B/glibc-2.31/stdlib/abort.c:81:7
#7 0x0000000002844064 llvm::report_fatal_error(llvm::Twine const&, bool) llvm/lib/Support/ErrorHandling.cpp:125:5
#8 0x0000000002843ed2 llvm/lib/Support/ErrorHandling.cpp:83:3
#9 0x0000000000eac075 llvm::RISCV_MC::verifyInstructionPredicates(unsigned int, llvm::FeatureBitset const&) build/lib/Target/RISCV/RISCVGenInstrInfo.inc:112254:1
#10 0x0000000000c69c4f (anonymous namespace)::RISCVAsmPrinter::emitInstruction(llvm::MachineInstr const*) llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp:228:3
#11 0x000000000126d58f llvm::AsmPrinter::emitFunctionBody() llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp:1735:13
#12 0x0000000000c69a72 (anonymous namespace)::RISCVAsmPrinter::runOnMachineFunction(llvm::MachineFunction&) llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp:376:7
#13 0x00000000016c14fc llvm::MachineFunctionPass::runOnFunction(llvm::Function&) llvm/lib/CodeGen/MachineFunctionPass.cpp:93:8
#14 0x0000000001eb850a llvm::FPPassManager::runOnFunction(llvm::Function&) llvm/lib/IR/LegacyPassManager.cpp:1435:23
#15 0x0000000001ebd332 llvm::FPPassManager::runOnModule(llvm::Module&) llvm/lib/IR/LegacyPassManager.cpp:1481:16
#16 0x0000000001eb8dbb (anonymous namespace)::MPPassManager::runOnModule(llvm::Module&) llvm/lib/IR/LegacyPassManager.cpp:1550:23
#17 0x0000000001eb893d llvm::legacy::PassManagerImpl::run(llvm::Module&) llvm/lib/IR/LegacyPassManager.cpp:535:16
#18 0x0000000001ebd611 llvm::legacy::PassManager::run(llvm::Module&) llvm/lib/IR/LegacyPassManager.cpp:1677:3
#19 0x0000000000c19c11 compileModule(char**, llvm::LLVMContext&) llvm/tools/llc/llc.cpp:743:41
#20 0x0000000000c17f2d main llvm/tools/llc/llc.cpp:416:13
#21 0x00007ffbd04ee083 __libc_start_main /build/glibc-SzIz7B/glibc-2.31/csu/../csu/libc-start.c:342:3
#22 0x0000000000c1770e _start (build/bin/llc+0xc1770e)
Aborted (core dumped)

I'm building from commit ID beffc821e8290136a1d8b359cc83487c359b48ca:

LLVM (http://llvm.org/):
LLVM version 18.0.0git
DEBUG build with assertions.
Default target:
Host CPU: znver2

Registered Targets:
riscv32 - 32-bit RISC-V
riscv64 - 64-bit RISC-V

</details>