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[DAG] computeKnownBits - ISD::ABS is zero in the high bits if the input has multiple sign bits #94344

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RKSimon opened this issue Jun 4, 2024 · 1 comment · Fixed by #94382
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llvm:SelectionDAG SelectionDAGISel as well

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RKSimon commented Jun 4, 2024

Alive2: https://alive2.llvm.org/ce/z/a87fHU

If the absolute value input is sign extended, then the absolute result is guaranteed to be zero in the (NumSignBits - 1) upper bits.

ISD::ABDS should be similar as well.

Noticed while working on #92576

@RKSimon RKSimon added the llvm:SelectionDAG SelectionDAGISel as well label Jun 4, 2024
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RKSimon commented Jun 4, 2024

ABDS alive: https://alive2.llvm.org/ce/z/7_z2Vc

RKSimon added a commit to RKSimon/llvm-project that referenced this issue Jun 4, 2024
RKSimon added a commit to RKSimon/llvm-project that referenced this issue Jun 4, 2024
…s sign-extended

As reported on llvm#94344 - if x has more than one signbit, then the upper bits of its absolute value are guaranteed to be zero

Alive2: https://alive2.llvm.org/ce/z/a87fHU
@RKSimon RKSimon self-assigned this Jun 4, 2024
RKSimon added a commit to RKSimon/llvm-project that referenced this issue Jun 5, 2024
RKSimon added a commit to RKSimon/llvm-project that referenced this issue Jun 5, 2024
…s sign-extended

As reported on llvm#94344 - if x has more than one signbit, then the upper bits of its absolute value are guaranteed to be zero

Alive2: https://alive2.llvm.org/ce/z/a87fHU
RKSimon added a commit that referenced this issue Jun 5, 2024
…s sign-extended (#94382)

As reported on #94344 - if x has more than one signbit, then the upper bits of its absolute value are guaranteed to be zero

Alive2: https://alive2.llvm.org/ce/z/a87fHU

Fixes #94344
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