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[AMDGPU] Adapt new lowering sequence for fdiv16 #109295

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[AMDGPU] Adapt new lowering sequence for fdiv16 #109295

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29 changes: 23 additions & 6 deletions llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4900,16 +4900,33 @@ bool AMDGPULegalizerInfo::legalizeFDIV16(MachineInstr &MI,
LLT S16 = LLT::scalar(16);
LLT S32 = LLT::scalar(32);

// a32.u = opx(V_CVT_F32_F16, a.u);
// b32.u = opx(V_CVT_F32_F16, b.u);
// r32.u = opx(V_RCP_F32, b32.u);
// q32.u = opx(V_MUL_F32, a32.u, r32.u);
// e32.u = opx(V_MAD_F32, (b32.u^_neg32), q32.u, a32.u);
// q32.u = opx(V_MAD_F32, e32.u, r32.u, q32.u);
// e32.u = opx(V_MAD_F32, (b32.u^_neg32), q32.u, a32.u);
// tmp.u = opx(V_MUL_F32, e32.u, r32.u);
// tmp.u = opx(V_AND_B32, tmp.u, 0xff800000);
// q32.u = opx(V_ADD_F32, tmp.u, q32.u);
// q16.u = opx(V_CVT_F16_F32, q32.u);
// q16.u = opx(V_DIV_FIXUP_F16, q16.u, b.u, a.u);

auto LHSExt = B.buildFPExt(S32, LHS, Flags);
auto RHSExt = B.buildFPExt(S32, RHS, Flags);

auto RCP = B.buildIntrinsic(Intrinsic::amdgcn_rcp, {S32})
auto NegRHSExt = B.buildFNeg(S32, RHSExt);
auto Rcp = B.buildIntrinsic(Intrinsic::amdgcn_rcp, {S32})
.addUse(RHSExt.getReg(0))
.setMIFlags(Flags);

auto QUOT = B.buildFMul(S32, LHSExt, RCP, Flags);
auto RDst = B.buildFPTrunc(S16, QUOT, Flags);

auto Quot = B.buildFMul(S32, LHSExt, Rcp);
auto Err = B.buildFMA(S32, NegRHSExt, Quot, LHSExt);
Quot = B.buildFMA(S32, Err, Rcp, Quot);
Err = B.buildFMA(S32, NegRHSExt, Quot, LHSExt);
auto Tmp = B.buildFMul(S32, Err, Rcp);
Tmp = B.buildAnd(S32, Tmp, B.buildConstant(S32, 0xff800000));
Quot = B.buildFAdd(S32, Tmp, Quot);
auto RDst = B.buildFPTrunc(S16, Quot, Flags);
B.buildIntrinsic(Intrinsic::amdgcn_div_fixup, Res)
.addUse(RDst.getReg(0))
.addUse(RHS)
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42 changes: 31 additions & 11 deletions llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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Expand Up @@ -10606,19 +10606,39 @@ SDValue SITargetLowering::LowerFDIV16(SDValue Op, SelectionDAG &DAG) const {
return FastLowered;

SDLoc SL(Op);
SDValue Src0 = Op.getOperand(0);
SDValue Src1 = Op.getOperand(1);

SDValue CvtSrc0 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src0);
SDValue CvtSrc1 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src1);

SDValue RcpSrc1 = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f32, CvtSrc1);
SDValue Quot = DAG.getNode(ISD::FMUL, SL, MVT::f32, CvtSrc0, RcpSrc1);
SDValue LHS = Op.getOperand(0);
SDValue RHS = Op.getOperand(1);

// a32.u = opx(V_CVT_F32_F16, a.u);
// b32.u = opx(V_CVT_F32_F16, b.u);
// r32.u = opx(V_RCP_F32, b32.u);
// q32.u = opx(V_MUL_F32, a32.u, r32.u);
// e32.u = opx(V_MAD_F32, (b32.u^_neg32), q32.u, a32.u);
// q32.u = opx(V_MAD_F32, e32.u, r32.u, q32.u);
// e32.u = opx(V_MAD_F32, (b32.u^_neg32), q32.u, a32.u);
// tmp.u = opx(V_MUL_F32, e32.u, r32.u);
// tmp.u = opx(V_AND_B32, tmp.u, 0xff800000);
// q32.u = opx(V_ADD_F32, tmp.u, q32.u);
// q16.u = opx(V_CVT_F16_F32, q32.u);
// q16.u = opx(V_DIV_FIXUP_F16, q16.u, b.u, a.u);

SDValue LHSExt = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, LHS);
SDValue RHSExt = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, RHS);
SDValue NegRHSExt = DAG.getNode(ISD::FNEG, SL, MVT::f32, RHSExt);
SDValue Rcp = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f32, RHSExt);
SDValue Quot = DAG.getNode(ISD::FMUL, SL, MVT::f32, LHSExt, Rcp);
SDValue Err = DAG.getNode(ISD::FMA, SL, MVT::f32, NegRHSExt, Quot, LHSExt);
Quot = DAG.getNode(ISD::FMA, SL, MVT::f32, Err, Rcp, Quot);
Err = DAG.getNode(ISD::FMA, SL, MVT::f32, NegRHSExt, Quot, LHSExt);
SDValue Tmp = DAG.getNode(ISD::FMUL, SL, MVT::f32, Err, Rcp);
SDValue TmpCast = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Tmp);
TmpCast = DAG.getNode(ISD::AND, SL, MVT::i32, TmpCast,
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I still don't understand this part, it's and by -infinity, so it's extracting the significand. Is it possible to use frexp_mant instead?

DAG.getTargetConstant(0xff800000, SL, MVT::i32));
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This is not a TargetConstant and should be a regular Constant

Tmp = DAG.getNode(ISD::BITCAST, SL, MVT::f32, TmpCast);
Quot = DAG.getNode(ISD::FADD, SL, MVT::f32, Tmp, Quot);
SDValue FPRoundFlag = DAG.getTargetConstant(0, SL, MVT::i32);
SDValue BestQuot = DAG.getNode(ISD::FP_ROUND, SL, MVT::f16, Quot, FPRoundFlag);

return DAG.getNode(AMDGPUISD::DIV_FIXUP, SL, MVT::f16, BestQuot, Src1, Src0);
SDValue RDst = DAG.getNode(ISD::FP_ROUND, SL, MVT::f16, Quot, FPRoundFlag);
return DAG.getNode(AMDGPUISD::DIV_FIXUP, SL, MVT::f16, RDst, RHS, LHS);
}

// Faster 2.5 ULP division that does not support denormals.
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