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[LLVM][AArch64] Add assembly/disassembly for FTMOPA and BFTMOPA #113230

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Oct 23, 2024
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[LLVM][AArch64] Add assembly/disassembly for FTMOPA and BFTMOPA #113230

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455b52c
[LLVM][AArch64] Add assembly/disassembly for FTMOPA and BFTMOPA
SpencerAbson Oct 21, 2024
ae825a3
Use ZPR_K register class in Decoder method
SpencerAbson Oct 22, 2024
6696a45
[NFC] Remove redundant comment from DecodeZK
SpencerAbson Oct 23, 2024
4e97faa
Merge branch 'main' into add-sme-tmopa
SpencerAbson Oct 23, 2024
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9 changes: 9 additions & 0 deletions llvm/lib/Target/AArch64/AArch64RegisterInfo.td
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Expand Up @@ -1210,6 +1210,15 @@ def ZPRMul2AsmOp32_Hi : ZPRAsmOperand<"VectorS_Hi", 32, "Mul2_Hi">;
def ZPRMul2AsmOp64_Lo : ZPRAsmOperand<"VectorD_Lo", 64, "Mul2_Lo">;
def ZPRMul2AsmOp64_Hi : ZPRAsmOperand<"VectorD_Hi", 64, "Mul2_Hi">;

def ZPR_K : RegisterClass<"AArch64", [untyped], 128,
(add Z20, Z21, Z22, Z23, Z28, Z29, Z30, Z31)>;

def ZK : RegisterOperand<ZPR_K, "printSVERegOp<>">{
let EncoderMethod = "EncodeZK";
let DecoderMethod = "DecodeZK";
let ParserMatchClass = ZPRAsmOperand<"Vector_20to23or28to31", 0, "_K">;
}

def ZPR8Mul2_Lo : ZPRMul2_MinToMaxRegOp<"b", ZPRMul2AsmOp8_Lo, 0, 14, ElementSizeB, ZPRMul2_Lo>;
def ZPR8Mul2_Hi : ZPRMul2_MinToMaxRegOp<"b", ZPRMul2AsmOp8_Hi, 16, 30, ElementSizeB, ZPRMul2_Hi>;
def ZPR16Mul2_Lo : ZPRMul2_MinToMaxRegOp<"h", ZPRMul2AsmOp16_Lo, 0, 14, ElementSizeH, ZPRMul2_Lo>;
Expand Down
21 changes: 21 additions & 0 deletions llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
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Expand Up @@ -1000,3 +1000,24 @@ defm FMOPA_MPPZZ_BtoS : sme_outer_product_fp32<0b0, 0b01, ZPR8, "fmopa", null_fr

} //[HasSMEF8F32]

let Predicates = [HasSME2p2] in {
def FTMOPA_M2ZZZI_HtoS : sme_tmopa_32b<0b11000, ZZ_h_mul_r, ZPR16, "ftmopa">;
def FTMOPA_M2ZZZI_StoS : sme_tmopa_32b<0b00000, ZZ_s_mul_r, ZPR32, "ftmopa">;
def BFTMOPA_M2ZZZI_HtoS : sme_tmopa_32b<0b10000, ZZ_h_mul_r, ZPR16, "bftmopa">;
} // [HasSME2p2]

let Predicates = [HasSME2p2, HasSMEB16B16] in {
def BFTMOPA_M2ZZZI_HtoH : sme_tmopa_16b<0b11001, ZZ_h_mul_r, ZPR16, "bftmopa">;
} // [HasSME2p2, HasSMEB16B16]

let Predicates = [HasSME2p2, HasSMEF8F32], Uses = [FPMR, FPCR] in {
def FTMOPA_M2ZZZI_BtoS : sme_tmopa_32b<0b01000, ZZ_b_mul_r, ZPR8, "ftmopa">;
} // [HasSME2p2, HasSMEF8F32], Uses = [FPMR, FPCR]

let Predicates = [HasSME2p2, HasSMEF8F16], Uses = [FPMR, FPCR] in {
def FTMOPA_M2ZZZI_BtoH : sme_tmopa_16b<0b01001, ZZ_b_mul_r, ZPR8, "ftmopa">;
} // [HasSME2p2, HasSMEF8F16], Uses = [FPMR, FPCR]

let Predicates = [HasSME2p2, HasSMEF16F16] in {
def FTMOPA_M2ZZZI_HtoH : sme_tmopa_16b<0b10001, ZZ_h_mul_r, ZPR16, "ftmopa">;
} // [HasSME2p2, HasSMEF16F16]
5 changes: 5 additions & 0 deletions llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
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Expand Up @@ -1264,6 +1264,7 @@ class AArch64Operand : public MCParsedAsmOperand {
case AArch64::ZPR_4bRegClassID:
case AArch64::ZPRMul2_LoRegClassID:
case AArch64::ZPRMul2_HiRegClassID:
case AArch64::ZPR_KRegClassID:
RK = RegKind::SVEDataVector;
break;
case AArch64::PPRRegClassID:
Expand Down Expand Up @@ -6118,6 +6119,9 @@ bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
case Match_InvalidZPRMul2_Hi64:
return Error(Loc, "Invalid restricted vector register, expected even "
"register in z16.d..z30.d");
case Match_InvalidZPR_K0:
return Error(Loc, "invalid restricted vector register, expected register "
"in z20..z23 or z28..z31");
case Match_InvalidSVEPattern:
return Error(Loc, "invalid predicate pattern");
case Match_InvalidSVEPPRorPNRAnyReg:
Expand Down Expand Up @@ -6827,6 +6831,7 @@ bool AArch64AsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
case Match_InvalidZPRMul2_Hi32:
case Match_InvalidZPRMul2_Lo64:
case Match_InvalidZPRMul2_Hi64:
case Match_InvalidZPR_K0:
case Match_InvalidSVEVectorList2x8Mul2:
case Match_InvalidSVEVectorList2x16Mul2:
case Match_InvalidSVEVectorList2x32Mul2:
Expand Down
16 changes: 16 additions & 0 deletions llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
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Expand Up @@ -49,6 +49,8 @@ template <unsigned Min, unsigned Max>
static DecodeStatus DecodeZPRMul2_MinMax(MCInst &Inst, unsigned RegNo,
uint64_t Address,
const MCDisassembler *Decoder);
static DecodeStatus DecodeZK(MCInst &Inst, unsigned RegNo, uint64_t Address,
const MCDisassembler *Decoder);
template <unsigned Min, unsigned Max>
static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address,
Expand Down Expand Up @@ -387,6 +389,20 @@ static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
return Success;
}

// Zk Is the name of the control vector register Z20-Z23 or Z28-Z31, encoded in
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// the "K:Zk" fields. Z20-Z23 = 000, 001,010, 011 and Z28-Z31 = 100, 101, 110,
// 111
static DecodeStatus DecodeZK(MCInst &Inst, unsigned RegNo, uint64_t Address,
const MCDisassembler *Decoder) {
if (RegNo > 7)
return Fail;

unsigned Register =
AArch64MCRegisterClasses[AArch64::ZPR_KRegClassID].getRegister(RegNo);
Inst.addOperand(MCOperand::createReg(Register));
return Success;
}

static DecodeStatus DecodeZPR4Mul4RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address,
const void *Decoder) {
Expand Down
22 changes: 22 additions & 0 deletions llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
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Expand Up @@ -195,6 +195,9 @@ class AArch64MCCodeEmitter : public MCCodeEmitter {
uint32_t EncodeRegMul_MinMax(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
uint32_t EncodeZK(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
uint32_t EncodePNR_p8to15(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
Expand Down Expand Up @@ -573,6 +576,25 @@ AArch64MCCodeEmitter::EncodeRegMul_MinMax(const MCInst &MI, unsigned OpIdx,
return (RegVal - Min) / Multiple;
}

// Zk Is the name of the control vector register Z20-Z23 or Z28-Z31, encoded in
// the "K:Zk" fields. Z20-Z23 = 000, 001,010, 011 and Z28-Z31 = 100, 101, 110,
// 111
uint32_t AArch64MCCodeEmitter::EncodeZK(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
auto RegOpnd = MI.getOperand(OpIdx).getReg();
unsigned RegVal = Ctx.getRegisterInfo()->getEncodingValue(RegOpnd);

// ZZ8-Z31 => Reg is in 3..7 (offset 24)
if (RegOpnd > AArch64::Z27)
return (RegVal - 24);

assert((RegOpnd > AArch64::Z19 && RegOpnd < AArch64::Z24) &&
"Expected ZK in Z20..Z23 or Z28..Z31");
// Z20-Z23 => Reg is in 0..3 (offset 20)
return (RegVal - 20);
}

uint32_t
AArch64MCCodeEmitter::EncodePNR_p8to15(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups,
Expand Down
62 changes: 62 additions & 0 deletions llvm/lib/Target/AArch64/SMEInstrFormats.td
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Expand Up @@ -3192,6 +3192,68 @@ multiclass sme2_int_bmopx_tile<string mnemonic, bits<3> op, SDPatternOperator i
def : SME_ZA_Tile_TwoPred_TwoVec_Pat<NAME, intrinsic, timm32_0_3, nxv4i1, nxv4i32>;
}

//===----------------------------------------------------------------------===//
// SME2 Sparse Outer Product and Accumulate

class sme_tmopa_16b<bits<5> opc, RegisterOperand zn_ty, RegisterOperand zm_ty, string mnemonic>
: I<(outs TileOp16:$ZAda),
(ins TileOp16:$_ZAda, zn_ty:$Zn, zm_ty:$Zm, ZK:$Zk, VectorIndexS32b:$imm),
mnemonic, "\t$ZAda, $Zn, $Zm, $Zk$imm",
"", []>,
Sched<[]> {
bit ZAda;
bits<4> Zn;
bits<5> Zm;
bits<3> Zk;
bits<2> imm;
let Inst{31-25} = 0b1000000;
let Inst{24} = opc{4};
let Inst{23-22} = 0b01;
let Inst{21} = opc{3};
let Inst{20-16} = Zm;
let Inst{15} = opc{2};
let Inst{14} = 0b0;
let Inst{13} = opc{1};
let Inst{12-10} = Zk;
let Inst{9-6} = Zn;
let Inst{5-4} = imm;
let Inst{3} = opc{0};
let Inst{2-1} = 0b00;
let Inst{0} = ZAda;

let Constraints = "$ZAda = $_ZAda";
}

class sme_tmopa_32b<bits<5> opc, RegisterOperand zn_ty, RegisterOperand zm_ty, string mnemonic>
: I<(outs TileOp32:$ZAda),
(ins TileOp32:$_ZAda, zn_ty:$Zn, zm_ty:$Zm, ZK:$Zk, VectorIndexS32b:$imm),
mnemonic, "\t$ZAda, $Zn, $Zm, $Zk$imm",
"", []>,
Sched<[]> {
bits<2> ZAda;
bits<4> Zn;
bits<5> Zm;
bits<3> Zk;
bits<2> imm;
let Inst{31-25} = 0b1000000;
let Inst{24} = opc{4};
let Inst{23-22} = 0b01;
let Inst{21} = opc{3};
let Inst{20-16} = Zm;
let Inst{15} = opc{2};
let Inst{14} = 0b0;
let Inst{13} = opc{1};
let Inst{12-10} = Zk;
let Inst{9-6} = Zn;
let Inst{5-4} = imm;
let Inst{3} = opc{0};
let Inst{2} = 0b0;
let Inst{1-0} = ZAda;

let Constraints = "$ZAda = $_ZAda";
}


//===----------------------------------------------------------------------===///
// SME2 Zero Lookup Table.
class sme2_zero_zt<string mnemonic, bits<4> opc>
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir
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Expand Up @@ -57,7 +57,7 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: inlineasm_virt_reg_output
; CHECK: INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, 2490378 /* regdef:FPR32_with_hsub_in_FPR16_lo */, def %0
; CHECK: INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, 2490378 /* regdef:GPR32common */, def %0
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY %0
; CHECK-NEXT: $w0 = COPY [[COPY]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
Expand All @@ -75,7 +75,7 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: inlineasm_virt_mixed_types
; CHECK: INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 2490378 /* regdef:FPR32_with_hsub_in_FPR16_lo */, def %0, 3342346 /* regdef:GPR64 */, def %1
; CHECK: INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 2490378 /* regdef:GPR32common */, def %0, 3342346 /* regdef:FPR64 */, def %1
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY %0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr(s64) = COPY %1
; CHECK-NEXT: $d0 = COPY [[COPY1]](s64)
Expand Down
14 changes: 7 additions & 7 deletions llvm/test/CodeGen/AArch64/aarch64-sve-asm.ll
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Expand Up @@ -13,7 +13,7 @@ define <vscale x 16 x i8> @test_svadd_i8(<vscale x 16 x i8> %Zn, <vscale x 16 x
; CHECK-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:zpr = COPY [[COPY1]]
; CHECK-NEXT: [[COPY3:%[0-9]+]]:zpr_3b = COPY [[COPY]]
; CHECK-NEXT: INLINEASM &"add $0.b, $1.b, $2.b", 0 /* attdialect */, 5701642 /* regdef:ZPR */, def %2, 5701641 /* reguse:ZPR */, [[COPY2]], 6291465 /* reguse:ZPR_3b */, [[COPY3]]
; CHECK-NEXT: INLINEASM &"add $0.b, $1.b, $2.b", 0 /* attdialect */, 5767178 /* regdef:ZPR */, def %2, 5767177 /* reguse:ZPR */, [[COPY2]], 6357001 /* reguse:ZPR_3b */, [[COPY3]]
; CHECK-NEXT: $z0 = COPY %2
; CHECK-NEXT: RET_ReallyLR implicit $z0
%1 = tail call <vscale x 16 x i8> asm "add $0.b, $1.b, $2.b", "=w,w,y"(<vscale x 16 x i8> %Zn, <vscale x 16 x i8> %Zm)
Expand All @@ -29,7 +29,7 @@ define <vscale x 2 x i64> @test_svsub_i64(<vscale x 2 x i64> %Zn, <vscale x 2 x
; CHECK-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:zpr = COPY [[COPY1]]
; CHECK-NEXT: [[COPY3:%[0-9]+]]:zpr_4b = COPY [[COPY]]
; CHECK-NEXT: INLINEASM &"sub $0.d, $1.d, $2.d", 0 /* attdialect */, 5701642 /* regdef:ZPR */, def %2, 5701641 /* reguse:ZPR */, [[COPY2]], 5963785 /* reguse:ZPR_4b */, [[COPY3]]
; CHECK-NEXT: INLINEASM &"sub $0.d, $1.d, $2.d", 0 /* attdialect */, 5767178 /* regdef:ZPR */, def %2, 5767177 /* reguse:ZPR */, [[COPY2]], 6029321 /* reguse:ZPR_4b */, [[COPY3]]
; CHECK-NEXT: $z0 = COPY %2
; CHECK-NEXT: RET_ReallyLR implicit $z0
%1 = tail call <vscale x 2 x i64> asm "sub $0.d, $1.d, $2.d", "=w,w,x"(<vscale x 2 x i64> %Zn, <vscale x 2 x i64> %Zm)
Expand All @@ -45,7 +45,7 @@ define <vscale x 8 x half> @test_svfmul_f16(<vscale x 8 x half> %Zn, <vscale x 8
; CHECK-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:zpr = COPY [[COPY1]]
; CHECK-NEXT: [[COPY3:%[0-9]+]]:zpr_3b = COPY [[COPY]]
; CHECK-NEXT: INLINEASM &"fmul $0.h, $1.h, $2.h", 0 /* attdialect */, 5701642 /* regdef:ZPR */, def %2, 5701641 /* reguse:ZPR */, [[COPY2]], 6291465 /* reguse:ZPR_3b */, [[COPY3]]
; CHECK-NEXT: INLINEASM &"fmul $0.h, $1.h, $2.h", 0 /* attdialect */, 5767178 /* regdef:ZPR */, def %2, 5767177 /* reguse:ZPR */, [[COPY2]], 6357001 /* reguse:ZPR_3b */, [[COPY3]]
; CHECK-NEXT: $z0 = COPY %2
; CHECK-NEXT: RET_ReallyLR implicit $z0
%1 = tail call <vscale x 8 x half> asm "fmul $0.h, $1.h, $2.h", "=w,w,y"(<vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm)
Expand All @@ -61,7 +61,7 @@ define <vscale x 4 x float> @test_svfmul_f(<vscale x 4 x float> %Zn, <vscale x 4
; CHECK-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:zpr = COPY [[COPY1]]
; CHECK-NEXT: [[COPY3:%[0-9]+]]:zpr_4b = COPY [[COPY]]
; CHECK-NEXT: INLINEASM &"fmul $0.s, $1.s, $2.s", 0 /* attdialect */, 5701642 /* regdef:ZPR */, def %2, 5701641 /* reguse:ZPR */, [[COPY2]], 5963785 /* reguse:ZPR_4b */, [[COPY3]]
; CHECK-NEXT: INLINEASM &"fmul $0.s, $1.s, $2.s", 0 /* attdialect */, 5767178 /* regdef:ZPR */, def %2, 5767177 /* reguse:ZPR */, [[COPY2]], 6029321 /* reguse:ZPR_4b */, [[COPY3]]
; CHECK-NEXT: $z0 = COPY %2
; CHECK-NEXT: RET_ReallyLR implicit $z0
%1 = tail call <vscale x 4 x float> asm "fmul $0.s, $1.s, $2.s", "=w,w,x"(<vscale x 4 x float> %Zn, <vscale x 4 x float> %Zm)
Expand All @@ -79,7 +79,7 @@ define <vscale x 8 x half> @test_svfadd_f16(<vscale x 16 x i1> %Pg, <vscale x 8
; CHECK-NEXT: [[COPY3:%[0-9]+]]:ppr_3b = COPY [[COPY2]]
; CHECK-NEXT: [[COPY4:%[0-9]+]]:zpr = COPY [[COPY1]]
; CHECK-NEXT: [[COPY5:%[0-9]+]]:zpr = COPY [[COPY]]
; CHECK-NEXT: INLINEASM &"fadd $0.h, $1/m, $2.h, $3.h", 0 /* attdialect */, 5701642 /* regdef:ZPR */, def %3, 655369 /* reguse:PPR_3b */, [[COPY3]], 5701641 /* reguse:ZPR */, [[COPY4]], 5701641 /* reguse:ZPR */, [[COPY5]]
; CHECK-NEXT: INLINEASM &"fadd $0.h, $1/m, $2.h, $3.h", 0 /* attdialect */, 5767178 /* regdef:ZPR */, def %3, 720905 /* reguse:PPR_3b */, [[COPY3]], 5767177 /* reguse:ZPR */, [[COPY4]], 5767177 /* reguse:ZPR */, [[COPY5]]
; CHECK-NEXT: $z0 = COPY %3
; CHECK-NEXT: RET_ReallyLR implicit $z0
%1 = tail call <vscale x 8 x half> asm "fadd $0.h, $1/m, $2.h, $3.h", "=w,@3Upl,w,w"(<vscale x 16 x i1> %Pg, <vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm)
Expand All @@ -95,7 +95,7 @@ define <vscale x 4 x i32> @test_incp(<vscale x 16 x i1> %Pg, <vscale x 4 x i32>
; CHECK-NEXT: [[COPY1:%[0-9]+]]:ppr = COPY $p0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:ppr = COPY [[COPY1]]
; CHECK-NEXT: [[COPY3:%[0-9]+]]:zpr = COPY [[COPY]]
; CHECK-NEXT: INLINEASM &"incp $0.s, $1", 0 /* attdialect */, 5701642 /* regdef:ZPR */, def %2, 393225 /* reguse:PPR */, [[COPY2]], 2147483657 /* reguse tiedto:$0 */, [[COPY3]](tied-def 3)
; CHECK-NEXT: INLINEASM &"incp $0.s, $1", 0 /* attdialect */, 5767178 /* regdef:ZPR */, def %2, 458761 /* reguse:PPR */, [[COPY2]], 2147483657 /* reguse tiedto:$0 */, [[COPY3]](tied-def 3)
; CHECK-NEXT: $z0 = COPY %2
; CHECK-NEXT: RET_ReallyLR implicit $z0
%1 = tail call <vscale x 4 x i32> asm "incp $0.s, $1", "=w,@3Upa,0"(<vscale x 16 x i1> %Pg, <vscale x 4 x i32> %Zn)
Expand All @@ -113,7 +113,7 @@ define <vscale x 8 x half> @test_svfadd_f16_Uph_constraint(<vscale x 16 x i1> %P
; CHECK-NEXT: [[COPY3:%[0-9]+]]:ppr_p8to15 = COPY [[COPY2]]
; CHECK-NEXT: [[COPY4:%[0-9]+]]:zpr = COPY [[COPY1]]
; CHECK-NEXT: [[COPY5:%[0-9]+]]:zpr = COPY [[COPY]]
; CHECK-NEXT: INLINEASM &"fadd $0.h, $1/m, $2.h, $3.h", 0 /* attdialect */, 5701642 /* regdef:ZPR */, def %3, 720905 /* reguse:PPR_p8to15 */, [[COPY3]], 5701641 /* reguse:ZPR */, [[COPY4]], 5701641 /* reguse:ZPR */, [[COPY5]]
; CHECK-NEXT: INLINEASM &"fadd $0.h, $1/m, $2.h, $3.h", 0 /* attdialect */, 5767178 /* regdef:ZPR */, def %3, 786441 /* reguse:PPR_p8to15 */, [[COPY3]], 5767177 /* reguse:ZPR */, [[COPY4]], 5767177 /* reguse:ZPR */, [[COPY5]]
; CHECK-NEXT: $z0 = COPY %3
; CHECK-NEXT: RET_ReallyLR implicit $z0
%1 = tail call <vscale x 8 x half> asm "fadd $0.h, $1/m, $2.h, $3.h", "=w,@3Uph,w,w"(<vscale x 16 x i1> %Pg, <vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm)
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir
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Expand Up @@ -91,10 +91,10 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[LOADgot:%[0-9]+]]:gpr64common = LOADgot target-flags(aarch64-got) @c
; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[LOADgot]], 0 :: (dereferenceable load (s64) from @c)
; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 3342346 /* regdef:GPR64 */, def %2, 2147483657 /* reguse tiedto:$0 */, [[LDRDui]](tied-def 3)
; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 3342346 /* regdef:FPR64 */, def %2, 2147483657 /* reguse tiedto:$0 */, [[LDRDui]](tied-def 3)
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY %2
; CHECK-NEXT: [[LDRDui1:%[0-9]+]]:fpr64 = LDRDui [[LOADgot]], 0 :: (dereferenceable load (s64) from @c)
; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 3342346 /* regdef:GPR64 */, def %4, 2147483657 /* reguse tiedto:$0 */, [[LDRDui1]](tied-def 3)
; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 3342346 /* regdef:FPR64 */, def %4, 2147483657 /* reguse tiedto:$0 */, [[LDRDui1]](tied-def 3)
; CHECK-NEXT: [[FNEGDr:%[0-9]+]]:fpr64 = FNEGDr %2
; CHECK-NEXT: nofpexcept FCMPDrr %4, killed [[FNEGDr]], implicit-def $nzcv, implicit $fpcr
; CHECK-NEXT: Bcc 1, %bb.2, implicit $nzcv
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AArch64/fmlal-loreg.ll
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Expand Up @@ -11,8 +11,8 @@ define <4 x float> @test(ptr %lhs_panel, ptr %rhs_panel, <4 x float> %a) {
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset b8, -16
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: ldr q8, [x0]
; CHECK-NEXT: ldr q16, [x1]
; CHECK-NEXT: ldr q8, [x0]
; CHECK-NEXT: lsr x9, x8, #32
; CHECK-NEXT: //APP
; CHECK-NEXT: nop
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AArch64/peephole-insvigpr.mir
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Expand Up @@ -487,7 +487,7 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[DEF]]
; CHECK-NEXT: INLINEASM &"ldr ${0:s}, $1", 8 /* mayload attdialect */, 3342346 /* regdef:GPR64 */, def %1, 262158 /* mem:m */, killed [[COPY1]]
; CHECK-NEXT: INLINEASM &"ldr ${0:s}, $1", 8 /* mayload attdialect */, 3342346 /* regdef:FPR64 */, def %1, 262158 /* mem:m */, killed [[COPY1]]
; CHECK-NEXT: [[MOVIv2d_ns:%[0-9]+]]:fpr128 = MOVIv2d_ns 0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[MOVIv2d_ns]].dsub
; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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