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Merge pull request #62 from LNIS-Projects/dev
Simplify fabric key where users just need to provide alias; start porting FPGA-SPICE
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Original file line number | Diff line number | Diff line change |
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/******************************************************************** | ||
* This file includes functions to compress the hierachy of routing architecture | ||
*******************************************************************/ | ||
/* Headers from vtrutil library */ | ||
#include "vtr_time.h" | ||
#include "vtr_log.h" | ||
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/* Headers from openfpgashell library */ | ||
#include "command_exit_codes.h" | ||
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#include "spice_api.h" | ||
#include "openfpga_spice.h" | ||
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/* Include global variables of VPR */ | ||
#include "globals.h" | ||
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/* begin namespace openfpga */ | ||
namespace openfpga { | ||
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/******************************************************************** | ||
* A wrapper function to call the fabric SPICE generator of FPGA-SPICE | ||
*******************************************************************/ | ||
int write_fabric_spice(OpenfpgaContext& openfpga_ctx, | ||
const Command& cmd, const CommandContext& cmd_context) { | ||
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CommandOptionId opt_output_dir = cmd.option("file"); | ||
CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping"); | ||
CommandOptionId opt_verbose = cmd.option("verbose"); | ||
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/* This is an intermediate data structure which is designed to modularize the FPGA-SPICE | ||
* Keep it independent from any other outside data structures | ||
*/ | ||
FabricSpiceOption options; | ||
options.set_output_directory(cmd_context.option_value(cmd, opt_output_dir)); | ||
options.set_explicit_port_mapping(cmd_context.option_enable(cmd, opt_explicit_port_mapping)); | ||
options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose)); | ||
options.set_compress_routing(openfpga_ctx.flow_manager().compress_routing()); | ||
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int status = CMD_EXEC_SUCCESS; | ||
status = fpga_fabric_spice(openfpga_ctx.module_graph(), | ||
openfpga_ctx.mutable_spice_netlists(), | ||
openfpga_ctx.arch().tech_lib, | ||
options); | ||
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return status; | ||
} | ||
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} /* end namespace openfpga */ |
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#ifndef OPENFPGA_SPICE_H | ||
#define OPENFPGA_SPICE_H | ||
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/******************************************************************** | ||
* Include header files that are required by function declaration | ||
*******************************************************************/ | ||
#include "command.h" | ||
#include "command_context.h" | ||
#include "openfpga_context.h" | ||
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/******************************************************************** | ||
* Function declaration | ||
*******************************************************************/ | ||
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/* begin namespace openfpga */ | ||
namespace openfpga { | ||
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int write_fabric_spice(OpenfpgaContext& openfpga_ctx, | ||
const Command& cmd, const CommandContext& cmd_context); | ||
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} /* end namespace openfpga */ | ||
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#endif |
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Original file line number | Diff line number | Diff line change |
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/******************************************************************** | ||
* Add commands to the OpenFPGA shell interface, | ||
* in purpose of generate SPICE netlists modeling the full FPGA fabric | ||
* This is one of the core engine of openfpga, including: | ||
* - generate_fabric_spice : generate Verilog netlists about FPGA fabric | ||
* - TODO: generate_spice_top_testbench : generate SPICE testbenches for top-level module | ||
* - TODO: generate_spice_grid_testbench : generate SPICE testbenches for grids | ||
* - TODO: generate_spice_cb_testbench : generate SPICE testbenches for connection blocks | ||
* - TODO: generate_spice_sb_testbench : generate SPICE testbenches for switch blocks | ||
* - TODO: generate_spice_lut_testbench : generate SPICE testbenches for Look-Up Tables | ||
* - TODO: generate_spice_hard_logic_testbench : generate SPICE testbenches for all the hard logics | ||
* - TODO: generate_spice_local_routing_testbench : generate SPICE testbenches for local routing | ||
* - TODO: generate_spice_cb_routing_testbench : generate SPICE testbenches for routing circuit inside connection blocks | ||
* - TODO: generate_spice_sb_routing_testbench : generate SPICE testbenches for routing circuit inside switch blocks | ||
*******************************************************************/ | ||
#include "openfpga_spice.h" | ||
#include "openfpga_spice_command.h" | ||
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/* begin namespace openfpga */ | ||
namespace openfpga { | ||
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/******************************************************************** | ||
* - Add a command to Shell environment: generate fabric Verilog | ||
* - Add associated options | ||
* - Add command dependency | ||
*******************************************************************/ | ||
static | ||
ShellCommandId add_openfpga_write_fabric_spice_command(openfpga::Shell<OpenfpgaContext>& shell, | ||
const ShellCommandClassId& cmd_class_id, | ||
const std::vector<ShellCommandId>& dependent_cmds) { | ||
Command shell_cmd("write_fabric_spice"); | ||
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/* Add an option '--file' in short '-f'*/ | ||
CommandOptionId output_opt = shell_cmd.add_option("file", true, "Specify the output directory for SPICE netlists"); | ||
shell_cmd.set_option_short_name(output_opt, "f"); | ||
shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING); | ||
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/* Add an option '--explicit_port_mapping' */ | ||
shell_cmd.add_option("explicit_port_mapping", false, "Use explicit port mapping in Verilog netlists"); | ||
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/* Add an option '--verbose' */ | ||
shell_cmd.add_option("verbose", false, "Enable verbose output"); | ||
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/* Add command 'write_fabric_spice' to the Shell */ | ||
ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "generate SPICE netlists modeling full FPGA fabric"); | ||
shell.set_command_class(shell_cmd_id, cmd_class_id); | ||
shell.set_command_execute_function(shell_cmd_id, write_fabric_spice); | ||
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/* Add command dependency to the Shell */ | ||
shell.set_command_dependency(shell_cmd_id, dependent_cmds); | ||
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return shell_cmd_id; | ||
} | ||
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void add_openfpga_spice_commands(openfpga::Shell<OpenfpgaContext>& shell) { | ||
/* Get the unique id of 'build_fabric' command which is to be used in creating the dependency graph */ | ||
const ShellCommandId& build_fabric_cmd_id = shell.command(std::string("build_fabric")); | ||
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/* Add a new class of commands */ | ||
ShellCommandClassId openfpga_spice_cmd_class = shell.add_command_class("FPGA-SPICE"); | ||
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/******************************** | ||
* Command 'write_fabric_spice' | ||
*/ | ||
/* The 'write_fabric_spice' command should NOT be executed before 'build_fabric' */ | ||
std::vector<ShellCommandId> fabric_spice_dependent_cmds; | ||
fabric_spice_dependent_cmds.push_back(build_fabric_cmd_id); | ||
add_openfpga_write_fabric_spice_command(shell, | ||
openfpga_spice_cmd_class, | ||
fabric_spice_dependent_cmds); | ||
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/******************************** | ||
* TODO: Command 'write_spice_top_testbench' | ||
*/ | ||
/* The command 'write_spice_top_testbench' should NOT be executed before 'build_fabric' */ | ||
} | ||
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} /* end namespace openfpga */ |
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,21 @@ | ||
#ifndef OPENFPGA_SPICE_COMMAND_H | ||
#define OPENFPGA_SPICE_COMMAND_H | ||
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/******************************************************************** | ||
* Include header files that are required by function declaration | ||
*******************************************************************/ | ||
#include "shell.h" | ||
#include "openfpga_context.h" | ||
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/******************************************************************** | ||
* Function declaration | ||
*******************************************************************/ | ||
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/* begin namespace openfpga */ | ||
namespace openfpga { | ||
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void add_openfpga_spice_commands(openfpga::Shell<OpenfpgaContext>& shell); | ||
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} /* end namespace openfpga */ | ||
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#endif |
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