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Memory, runtime and netlist size optimization #58

Merged
merged 23 commits into from
Jul 1, 2020
Merged

Memory, runtime and netlist size optimization #58

merged 23 commits into from
Jul 1, 2020

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tangxifan
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@tangxifan tangxifan commented Jul 1, 2020 •
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Multiple improvements:

  • Reduce the memory footprint of the module manager data structure by 2x on large FPGA fabrics
  • Use bus ports in routing modules, i.e., SBs and CBs, which significantly reduce the netlist size.
  • Improve fabric key file format to be more friendly for engineering (allow the definition of instance names)
  • Other improvements on the simulation ini file content to support UVM

@tangxifan
add verbose output to edge sorting for GSBs
ebf5636
@tangxifan
add alias name support for fabric key
9d32a5b
@tangxifan
update sample key
b2fb5f7
@tangxifan
update documentation about alias support in fabric key
933801c
@tangxifan
optimizing the constant writing in Verilog for single bits
e993795
@tangxifan
optimizing memory efficiency by reserving nets in module manager
66746f6
@tangxifan
add reserve net sources and sinks to module manager
57e6c84
@tangxifan
add profile time to top module builder for better spot on runtime/mem…
e7d5736 
…ory overhead sources
@tangxifan
use efficient net builder in top module connection builder
025d4a3
@tangxifan
use more robust net builder in inter tile connections
23bcad0
@tangxifan
optimize memory efficiency for module net id storage
f49cabe
@tangxifan
keep optimizing memory footprint of module manager by using net termi…
f023652 
…nal storage
@tangxifan
adapt SB module builder to use bus ports
2ef083c
@tangxifan
adapt bus ports in connection block module builder
2e7684b
@tangxifan
use typedef to short the module pin information
05187f8
@tangxifan
use easy-to-access net look up in switch block module builder
1015880
@tangxifan
add readme for architecture file naming
20cf4ac
@tangxifan
add readme for OpenFPGA architecture naming
73e75bf
@tangxifan
update fabric bitstream writer to support various configuration proto…
e688ca1 
…cols
@tangxifan
add additional information in the simulation ini file for UVM
b74dde9
@tangxifan
bug fix in simulation ini GPIO width
cb2baed
@tangxifan
now split CB module bus ports into lower/upper parts
0a3c746
@tangxifan
add comments to clarify how to select CB ports when connecting to SBs…
81ecfa3 
… at the top level
@tangxifan tangxifan merged commit 06d4667 into master Jul 1, 2020
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