Bump yosys-plugins from 6d51ff0 to 8dbda8d
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Bumps [yosys-plugins](https://github.com/SymbiFlow/yosys-symbiflow-plugins) from `6d51ff0` to `8dbda8d`. - [Release notes](https://github.com/SymbiFlow/yosys-symbiflow-plugins/releases) - [Commits](chipsalliance/yosys-f4pga-plugins@6d51ff0...8dbda8d) --- updated-dependencies: - dependency-name: yosys-plugins dependency-type: direct:production ... Signed-off-by: dependabot[bot] <support@github.com>
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Bumps yosys-plugins from
6d51ff0to8dbda8d.Commits
8dbda8dMerge pull request #263 from antmicro/pcza/ql-qlf-k6n10f-tdp-inference862ec6bql-qlf: qlf_k6n10f: bram: sim: switch RAM_ID from parameter to port97fbb80ql-qlf: qlf_k6n10f: bram: techmap: switch RAM_ID from parameter to port41084deql-qlf: qlf_k6n10f: bram: techmap: cleanup R/WMODES2f7695eql-qlf: qlf_k6n10f: bram: techmap: rearrange portsbf82038ql-qlf: qlf_k6n10f: bram: add post synthesis simulation testse3cbd48Merge pull request #264 from rakeshm75/update_cells_sim9d61b87tests: introduce post synthesis simulation infrastructuref7ab627ql-qlf: qlf_k6n10f: bram: introduce TDP synthesis test casesd84e8edql-qlf: qlf_k6n10f: bram: use 4 port matching rules to enable TDP RAM inferenceDependabot will resolve any conflicts with this PR as long as you don't alter it yourself. You can also trigger a rebase manually by commenting
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