Support Negative Edge Flip-flop

.github/workflows/cell_lib_test.yml

@@ -0,0 +1,40 @@
+name: Cell Library Tests
+
+# Run CI on push, PR, and weekly.
+
+on:
+  push:
+  pull_request:
+  schedule:
+    - cron: "0 0 * * 0 " # weekly
+
+# Multiple job to tests
+jobs:
+  # Test the RTL compilation compatibility
+  verilog:
+    name: RTL compilation and tests
+    runs-on: ubuntu-18.04
+    steps:
+      - name: Cancel previous
+        uses: styfle/cancel-workflow-action@0.9.1
+        with:
+          access_token: ${{ github.token }}
+
+      - name: Checkout OpenFPGA repo
+        uses: actions/checkout@v2
+        with:
+          submodules: true
+
+      - name: Install Dependencies
+        run: |
+          sudo bash .github/workflows/install_dependencies_run.sh
+
+      - name: Dump tool versions
+        run: |
+          iverilog -V
+          vvp -V
+
+      - name: Verilog compilation
+        run: |
+          cd openfpga_flow/openfpga_cell_library
+          make compile_verilog 

openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_negedge_async_reset/counter.v

@@ -0,0 +1,29 @@
+///////////////////////////////////////////
+//  Functionality: Counter triggered at negative edge with asynchronous reset
+//  Author:        Xifan Tang
+////////////////////////////////////////
+
+module counter (
+	clkn,
+	reset,
+	result
+);
+
+	input clkn;
+	input reset;
+	output [7:0] result;
+
+	reg [7:0] result;
+
+    initial begin
+      result <= 0;
+    end
+
+	always @(negedge clkn or posedge reset)
+	begin
+		if (reset) 
+			result = 0;		
+		else 
+			result = result + 1;
+	end
+endmodule		

openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_negedge_async_reset/counter_tb.v

@@ -0,0 +1,25 @@
+module counter_tb;
+
+  reg clk, reset;
+  wire [7:0] result;
+
+  counter DUT(
+    .clkn(clk), 
+    .reset(reset), 
+    .result(result)
+  );
+
+  initial begin
+    #0 reset = 1'b1; clk = 1'b0;
+    #100 reset = 1'b0;
+  end
+
+  always begin
+    #10 clk = ~clk;
+  end
+
+  initial begin
+    #5000 $stop;
+  end
+
+endmodule

openfpga_flow/openfpga_arch/README.md

@@ -6,7 +6,7 @@ Note that an OpenFPGA architecture can be applied to multiple VPR architecture f
   * The keyword 'frac' is to specify if fracturable LUT is used or not.
   * The keyword 'Native' is to specify if fracturable LUT design is a native one (without mode switch) or a standard one (with mode switch).
 - N<le\_size>: Number of logic elements for a CLB. If you have multiple CLB architectures, this should be largest number.
-- fracdff: Use multi-mode DFF model, where reset/set/clock polarity is configurable
+- fracff<2edge>: Use multi-mode flip-flop model, where reset/set polarity is configurable. When 2edge is specified, clock polarity can be switched between postive edge triggered and negative edge triggered
 - adder\_chain: If hard adder/carry chain is used inside CLBs
 - register\_chain: If shift register chain is used inside CLBs
 - scan\_chain: If scan chain testing infrastructure is used inside CLBs

openfpga_flow/openfpga_cell_library/Makefile

@@ -0,0 +1,29 @@
+# 
+# OpenFPGA cell library Makefile
+# ==============================
+# 
+# Check correctness of the cell library files
+
+SHELL = bash
+PYTHON_EXEC ?= python3
+
+# Put it first so that "make" without argument is like "make help".
+export COMMENT_EXTRACT
+
+# Put it first so that "make" without argument is like "make help".
+help:
+	@${PYTHON_EXEC} -c "$$COMMENT_EXTRACT"
+
+compile_verilog:
+# This command checks the compile compatibility of Verilog files
+	for f in `cat verilog_sources.f`; do iverilog $$f; done 
+
+# Functions to extract comments from Makefiles
+define COMMENT_EXTRACT
+import re
+with open ('Makefile', 'r' ) as f:
+    matches = re.finditer('^([a-zA-Z-_]*):.*\n#(.*)', f.read(), flags=re.M)
+    for _, match in enumerate(matches, start=1):
+        header, content = match[1], match[2]
+        print(f"  {header:10} {content}")
+endef

openfpga_flow/openfpga_cell_library/verilog/dff.v

@@ -294,6 +294,33 @@ DFFRQ FF_CORE (.RST(post_rst),
 
 endmodule //End Of Module
 
+//-----------------------------------------------------
+// Function : A multi-functional D-type flip-flop with 
+//           - asynchronous reset 
+//             which can be switched between active-low and active high
+//           - clock
+//             which can be switched between positive edge triggered and negative edge triggered
+//-----------------------------------------------------
+module MULTI_MODE_DFFNRQ (
+  input RST, // Reset input
+  input CK, // Clock Input
+  input D, // Data Input
+  output Q, // Q output
+  input [0:1] mode // mode-selection bits: bit0 for reset polarity; bit1 for set polarity
+);
+
+wire post_rst = mode[0] ? ~RST : RST;
+wire post_clk = mode[1] ? ~CK : CK;
+
+DFFRQ FF_CORE (.RST(post_rst),
+               .CK(post_clk),
+               .D(D),
+               .Q(Q)
+               );
+
+endmodule //End Of Module
+
+
 //-----------------------------------------------------
 // Function    : D-type flip-flop with 
 //               - asynchronous active high reset

openfpga_flow/openfpga_cell_library/verilog_sources.f

@@ -0,0 +1,23 @@
+verilog/adder.v
+verilog/aib.v
+verilog/buf4.v
+verilog/dff.v
+verilog/dpram.v
+verilog/dpram16k.v
+verilog/dpram1k.v
+verilog/dpram8k.v
+verilog/dpram_2048x8.v
+verilog/frac_mem_32k.v
+verilog/frac_mult_16x16.v
+verilog/gpio.v
+verilog/inv.v
+verilog/latch.v
+verilog/lut6.v
+verilog/mult_32x32.v
+verilog/mult_36x36.v
+verilog/mult_8x8.v
+verilog/mux2.v
+verilog/or2.v
+verilog/spram_4x1.v
+verilog/sram.v
+verilog/tap_buf4.v

openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v

@@ -47,12 +47,12 @@ endmodule
 // The following techmap operation are not performed right now
 // as Negative edge FF are not legalized in synth_quicklogic for qlf_k6n10
 // but in case we implement clock inversion in the future, the support is ready for it.
-module \$_DFF_N_ (D, C, Q);
+module \$_DFF_N_ (D, CN, Q);
     input D;
-    input C;
+    input CN;
     output Q;
     parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
-    dff #(.IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C));
+    dff #(.IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(CN));
 endmodule
 
 module \$_DFF_NP0_ (D, C, R, Q);
@@ -61,7 +61,7 @@ module \$_DFF_NP0_ (D, C, R, Q);
     input R;
     output Q;
     parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
-    dffr #(.IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R));
+    dffnr #(.IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.Q(Q), .D(D), .CN(C), .R(R));
 endmodule
 
 module  \$_DFFE_NP0P_ (D, C, E, R, Q);

openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v

@@ -47,6 +47,34 @@ module dffr(
     endcase
 endmodule
 
+(* abc9_flop, lib_whitebox *)
+module dffnr(
+    output reg Q,
+    input D,
+    input R,
+    (* clkbuf_sink *)
+    (* invertible_pin = "IS_C_INVERTED" *)
+    input CN
+);
+    parameter [0:0] INIT = 1'b0;
+    parameter [0:0] IS_C_INVERTED = 1'b0;
+    initial Q = INIT;
+    case(|IS_C_INVERTED)
+          1'b0:
+            always @(posedge CN or posedge R)
+                if (R == 1'b1)
+                        Q <= 1'b0;
+                else
+                        Q <= D;
+          1'b1:
+            always @(negedge CN or posedge R)
+                if (R == 1'b1)
+                        Q <= 1'b0;
+                else
+                        Q <= D;
+    endcase
+endmodule
+
 (* abc9_flop, lib_whitebox *)
 module dffre(
     output reg Q,

openfpga_flow/regression_test_scripts/basic_reg_test.sh

@@ -110,6 +110,8 @@ echo -e "Testing K4N4 with facturable LUTs";
 run-task basic_tests/k4_series/k4n4_frac_lut --debug --show_thread_logs
 echo -e "Testing K4N4 with asynchronous reset";
 run-task basic_tests/k4_series/k4n4_fracff --debug --show_thread_logs
+echo -e "Testing K4N4 with negative edge clocks";
+run-task basic_tests/k4_series/k4n4_fracff2edge --debug --show_thread_logs
 echo -e "Testing K4N4 with hard adders";
 run-task basic_tests/k4_series/k4n4_adder --debug --show_thread_logs
 echo -e "Testing K4N4 without local routing architecture";
@@ -185,4 +187,4 @@ run-task template_tasks/vtr_benchmarks_template --debug --show_thread_logs
 
 echo -e "Testing create tsk from template and run task"
 create-task _task_copy basic_tests/generate_fabric
-run-task _task_copy
+run-task _task_copy

openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff2edge/config/pin_constraints_reset.xml

@@ -0,0 +1,8 @@
+<pin_constraints>
+  <!-- For a given .blif file, we want to assign 
+       - the reset signal to the op_reset[0] port of the FPGA fabric
+    -->
+  <set_io pin="op_reset[0]" net="reset"/>
+  <set_io pin="clk[0]" net="clkn"/>
+</pin_constraints>
+

openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff2edge/config/task.conf

@@ -0,0 +1,42 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = false
+spice_output=false
+verilog_output=true
+timeout_each_job = 3*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_without_ace_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff2edge_40nm_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff2edge_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_negedge_async_reset/counter.v
+
+[SYNTHESIS_PARAM]
+# Yosys script parameters
+bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v
+bench_yosys_dff_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v
+bench_read_verilog_options_common = -nolatches
+bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys
+bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
+
+bench0_top = counter
+bench0_openfpga_pin_constraints_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff2edge/config/pin_constraints_reset.xml
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=

openfpga_flow/vpr_arch/README.md

@@ -7,7 +7,7 @@ Please reveal the following architecture features in the names to help quickly s
 - N<le\_size>: Number of logic elements for a CLB. If you have multiple CLB architectures, this should be largest number.
 - tileable<IO>: If the routing architecture is tileable or not. 
   * The keyword 'IO' specifies if the I/O tile is tileable or not
-- fracdff: Use multi-mode DFF model, where reset/set/clock polarity is configurable
+- fracff<2edge>: Use multi-mode flip-flop model, where reset/set polarity is configurable. When 2edge is specified, clock polarity can be switched between postive edge triggered and negative edge triggered
 - adder\_chain: If hard adder/carry chain is used inside CLBs
 - register\_chain: If shift register chain is used inside CLBs
 - scan\_chain: If scan chain testing infrastructure is used inside CLBs