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Fix tileable rr graph read/write issue. #680

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merged 3 commits into from
Jun 24, 2022

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Yitian4Debug
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Motivate of the pull request

  • To address an existing issue in tileable rr_graph read/write
  • Breaking new feature. If so, please describe details in the description part.

Describe the technical details

What is currently done? (Provide issue link if applicable)

Currently, OpenFPGA has the following limitations:

  • PTC data written out tileable rr graph can't be read in successfully

What does this pull request change?

-- This PR improves in the following aspects:

  • Add function to read in PTC data in tileable rr graph

Which part of the code base require a change

  • VPR
  • Tileable routing architecture generator
  • OpenFPGA libraries
  • FPGA-Verilog
  • FPGA-Bitstream
  • FPGA-SDC
  • FPGA-SPICE
  • Flow scripts
  • Architecture library
  • Cell library
  • Documentation
  • Regression tests
  • Continous Integration (CI) scripts

Impact of the pull request

  • Require a change on Quality of Results (QoR)
  • Break back-compatibility. If so, please list who may be influenced.

@github-actions github-actions bot added the VPR label Jun 6, 2022
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@tangxifan tangxifan left a comment

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@taoli4rs Need to generalize the code changes which may cause problems for many other architectures. We should not limit users when architecting FPGAs.

Also, we miss regression tests to validate the correctness of this feature.
My suggestion is to create a new test case where

  • In openfpga shell, you call vpr's analysis only flow. You run verilog-to-verification flow as other test cases:

https://github.com/lnis-uofu/OpenFPGA/blob/master/openfpga_flow/tasks/basic_tests/preconfig_testbench/configuration_chain/config/task.conf

if you want to define input files for VPR, please consider to use the variables like

openfpga_vpr_device_layout=--device 2x2 --route_chan_width 40

vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route ${OPENFPGA_VPR_DEVICE_LAYOUT}

@@ -47,6 +47,7 @@ static void process_nodes(std::ifstream& fp, ClusterNetId inet, const char* file
static void process_nets(std::ifstream& fp, ClusterNetId inet, std::string name, std::vector<std::string> input_tokens, const char* filename, int& lineno);
static void process_global_blocks(std::ifstream& fp, ClusterNetId inet, const char* filename, int& lineno);
static void format_coordinates(int& x, int& y, std::string coord, ClusterNetId net, const char* filename, const int lineno);
static void format_ptc_num(int& n0, int& n1, int& n2, int& n3, std::string coord, ClusterNetId net, const char* filename, const int lineno);
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Be careful. This is a corner case. You see 4 ptc numbers because of the use of Length-4 wires. Users are free to define any length of wires as supported by tileable rr_graph.
So I suggest to use a vector.

if (device_ctx.rr_graph.node_ptc_num(node) != ptc) {
int ptc0, ptc1, ptc2, ptc3;
format_ptc_num(ptc0, ptc1, ptc2, ptc3, tokens[5 + offset], inet, filename, lineno);
if (device_ctx.rr_graph.node_ptc_num(node) != ptc0) {
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Need a double check on the selection of ptc number. I forgot if we should always use the first one or the last one. For nodes whose direction is INC_DIR, I think we should use the first one. However, for the nodes whose direction is DEC_DIR, please double check if this is true or not.

size_t ptc_count = std::count(ptc_str.begin(), ptc_str.end(), ',') + 1;
// detect and remove the parenthesis
std::stringstream ptc_stream(ptc_count > 1? format_name(ptc_str) : ptc_str);
for (size_t i = 0; i < ptc_count; i++) {
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@tangxifan tangxifan self-requested a review June 14, 2022 03:06
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@taoli4rs Please update regression tests in follow PRs.
Merge it now.

@tangxifan tangxifan merged commit 2168321 into master Jun 24, 2022
@tangxifan tangxifan deleted the tileable_rr_graph_read_write_fix branch June 24, 2022 00:45
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