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Misc Updates #70

Merged
merged 11 commits into from
Jul 24, 2020
Merged

Misc Updates #70

merged 11 commits into from
Jul 24, 2020

Commits on Jul 23, 2020

  1. add spice support on power gated inverters

    @tangxifan
    tangxifan committed Jul 23, 2020
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  2. move check codes on power gate ports to libarchopenfpga 

    Try to report errors to users as early as possible
    @tangxifan
    tangxifan committed Jul 23, 2020
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  3. support multi-bit power gate ports in FPGA-SPICE

    @tangxifan
    tangxifan committed Jul 23, 2020
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  4. add power gate example architecture

    @tangxifan
    tangxifan committed Jul 23, 2020
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  5. add power gate inverter test case (full testbench)

    @tangxifan
    tangxifan committed Jul 23, 2020
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  6. bug fix in power gating support of FPGA-Verilog

    @tangxifan
    tangxifan committed Jul 23, 2020
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  7. deploy power gating test cases to CI

    @tangxifan
    tangxifan committed Jul 23, 2020
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  8. update openfpga architecture README for power-gating

    @tangxifan
    tangxifan committed Jul 23, 2020
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Commits on Jul 24, 2020

  1. formulate file name, module name and instance name to be consistent

    @tangxifan
    tangxifan committed Jul 24, 2020
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  2. split logical tile netlists to keep good Verilog hierarchy

    @tangxifan
    tangxifan committed Jul 24, 2020
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  3. update fabric key to synchronize with new module/instance naming

    @tangxifan
    tangxifan committed Jul 24, 2020
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