This is my design and implementation of a two-pipelined CPU for the RISC-V instruction set architecture using digital logic circuits simulated in Logisim. This CPU is capable of converting RISC-V assembly code into runnable machine code. I implemented multiple essential components including an arithmetic logic unit (ALU), a control unit, ROM input, and memory hierarchy. Additionally, pipelining and control hazards are addressed through forwarding and stall mechanisms for correct instruction execution at each time step.
This project was completed with my partner, Daisy Polanco, as part of UC Berkeley's Computer Architecture and Machine Structures course.
The full project specifications can be found here: https://inst.eecs.berkeley.edu/~cs61c/su21/projects/proj3/