Update dependency at_clifford_yosys2 to v0.48

[renovate]

This PR contains the following updates:

Package	Type	Update	Change
at_clifford_yosys2	http_archive	minor	yosys-0.44 -> v0.48

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Release Notes

YosysHQ/yosys (at_clifford_yosys2)

v0.48: Yosys 0.48

Compare Source

Yosys 0.47 .. Yosys 0.48

• Various

  • Removed "read_ilang" deprecated pass.
  • Enhanced boxing features in the experimental "abc_new" command.
  • Added new Tcl methods for design inspection.
  • Added clock enable inference to "dfflibmap".
  • Added a Han-Carlson and Sklansky option for $lcu mapping.

• New commands and options

  • Added "-nopeepopt" option to "clk2fflogic" pass.
  • Added "-liberty" and "-dont_use" options to "clockgate" pass.
  • Added "-ignore_buses" option to "read_liberty" pass.
  • Added "-dont_map" option to "techmap" pass.
  • Added "-selected" option to "write_json" pass.
  • Added "wrapcell" command for creating wrapper modules
    around selected cells.
  • Added "portarcs" command for deriving propagation timing arcs.
  • Added "setenv" command for setting environment variables.

• Gowin support

  • Added "-family" option to "synth_gowin" pass.
  • Cell definitions split by family.

• Verific support

  • Improved blackbox support.

v0.47

Compare Source

• Various

  • Removed "read_ilang" deprecated pass.
  • Enhanced boxing features in the experimental "abc_new" command.
  • Added new Tcl methods for design inspection.
  • Added clock enable inference to "dfflibmap".
  • Added a Han-Carlson and Sklansky option for $lcu mapping.

• New commands and options

  • Added "-nopeepopt" option to "clk2fflogic" pass.
  • Added "-liberty" and "-dont_use" options to "clockgate" pass.
  • Added "-ignore_buses" option to "read_liberty" pass.
  • Added "-dont_map" option to "techmap" pass.
  • Added "-selected" option to "write_json" pass.
  • Added "wrapcell" command for creating wrapper modules
    around selected cells.
  • Added "portarcs" command for deriving propagation timing arcs.
  • Added "setenv" command for setting environment variables.

• Gowin support

  • Added "-family" option to "synth_gowin" pass.
  • Cell definitions split by family.

• Verific support

  • Improved blackbox support.

v0.46

Compare Source

• Various

  • Added cxxopts library for handling command line arguments.
  • Added docs generation from cells help output.

• New commands and options

  • Added "-json" option to "synth_xilinx" pass.
  • Added "-derive_luts" option to "cellmatch" pass.
  • Added "t:@​" syntax to "select" pass.
  • Added "-list-mod" option to "select" pass.
  • Removed deprecated "qwp" pass.

• Verific support

  • Initial state handling for VHDL assertions.

v0.45

Compare Source

• Various

  • Added new "functional backend" infrastructure with three example
    backends (C++, SMTLIB and Rosette).
  • Added new coarse-grain buffer cell type "$buf" to RTLIL.
  • Added "-y" command line option to execute a Python script with
    libyosys available as a built-in module.
  • Added support for casting to type in Verilog frontend.

• New commands and options

  • Added "clockgate" pass for automatic clock gating cell insertion.
  • Added "bufnorm" experimental pass to convert design into
    buffered-normalized form.
  • Added experimental "aiger2" and "xaiger2" backends, and an
    experimental "abc_new" command
  • Added "-force-detailed-loop-check" option to "check" pass.
  • Added "-unit_delay" option to "read_liberty" pass.

• Verific support

  • Added left and right bound properties to wires when using
    specific VHDL types.

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