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Pins GPIO9 and GPIO10

M Hightower edited this page Aug 15, 2024 · 80 revisions

Using GPIO9 and GPIO10 on ESP-12F Module or NodeMCU 1.0

Please look at the library SpiFlashUtils for my solution. In most cases, this solution should work for the ESP-12F Module and the NodeMCU 1.0 DEV board; however, It all depends on the SPI flash chip the module manufacturer selected. The few I have are working. I assume that board vendors that expose GPIO pins 9 and 10 have made wise choices with their flash chip selection. Allowing the pin functions /WP and /HOLD to be disabled. I am cautiously optimistic about this solution. Confidence will only come with experience.

To increase my pool of devices for testing, I used the few ESP-01 boards I had on hand. These did not do as well. One of these ESP-01 vendors had chosen a flash memory part that shorted /HOLD to Vcc. I was not expecting to find that.

Pin Name Clarifications and Terms:

  • GPIO9, /HOLD, Flash SD3, Espressif SD_D2, and IO3 all refer to the same connection, but from different perspectives.

  • GPIO10, /WP, Flash SD2, Espressif SD_D3, and IO2 all refer to the same connection, but from different perspectives.

  • The ESP8266 mux decides if the SPI0 controller has the pin connection or if the GPIO has the pin. You alter this assignment when you call pinMode. Example pinMode(9, SPECIAL) assigns the connection to the SPI0 controller. Where, pinMode(9, OUTPUT) connects to a GPIO output function or pinMode(9, INPUT) connects to a GPIO input function.

  • Quad Enable, QE, is a bit in the Flash Status Register. When QE is set, pin functions /WP and /HOLD are disabled. This allows the Chip to reuse those pins in SPI Modes QIO or QOUT without creating conflicts.

  • SRP1 and SRP0 refer to Status Register Protect-1 and Status Register Protect-0. Not all flash memory implements these bits; however, when they do, SRP1:SRP0 may implement an ignore /WP function.

  • SR1, SR2, and SR3 refer to 8-bit SPI Status Registers 1, 2, and 3.

  • S6, S9, and S15 refer to bits in the SPI Flash Status Registers. SR1 bits 0 - 7 are S0 - S7. SR2 bits 0 - 7 are S8 - S15.

duplicate

A Review of Past Attempts

Over the years, attempts to reclaim GPIO9 and GPIO10 have centered around hardware modifications: cutting traces, lifting pads, strapping /WP, and /HOLD Flash pins to +V directly or through pull-up resistors. If you do this, always use a pullup resistor.

With an unmodified EPS-12E or NodeMCU, some report that GPIO10 works; however, GPIO9 caused WDT Resets.

And some clippings from Gitter:

StanJ @Tech-TX Feb 24 16:02, February 22, 2021 2:51 AM

IF and only if the module/flash is wired for it AND you've programmed the flash in DIO mode, you might be able to use GPIO10? for input. It's very rare that anyone gets it to work. There's also the possibility that you can use that Flash SPI port in 'Overlap Mode' with LCDs, but again it's rare that people get it to work.

Develo @devyte Feb 24 17:05

On the esp12 gpio 9 and 10 are hard-wired to the flash. Whether they are usable or not depends on several things, including the flash brand. Attempting to use them blindly can crash the esp, damage the esp, damage the flash, all of the previous, or none of the previous. There is no guide that provides specifics. If using them is a necessity, there is only one safe solution: you need to open the shield and cut the two PCB tracks that lead to the flash, leaving the esp tracks connected, then change to DIO mode. QIO is then obviously no longer viable. That assumes that your flash supports DIO. The other pins on that edge are not usable for gpio afaik.

Develo said, "There is no guide that provides specifics." The goal here is to provide some guidance. What has worked, why, and hopefully, enough details to make it repeatable.

Why does GPIO10 work and not GPIO9?

GPIO10 is connected to the /WP pin on the SPI Flash. Yet in many cases, it works as a GPIO pin without any issue on many devices. For the why? We focus on SPI Flash Status Register's BIT8 and BIT7 in the Flash memory datasheet. When these bits are 0, pin /WP is ignored. And, this tends to be the factory default. Confirmed with datasheets for: W25Q32 bits SRL:SRP=0:0, GD25Q32C bits SRP1:SRP0=0:0, XM25Q32C SRP1:SRP0=0:0. However, not all Flash memory is the same. For example, EN25Q32C is different; It has only one status register and no QE bit. (more later on QE bit) It does have a Status Register BIT6, WPDis, to disable pin function /WP. And, the pin function /HOLD does not exist on this part only an SD3 pin.

It is easy to see why GPIO9 does not work. For the case SPI Flash Mode: "DIO", when the Flash pin /HOLD is active, the Flash chip's SPI bus operation is put on hold (stopped) allowing for a higher priority bus activity. When held on hold too long, as in the case of the GPIO9 set LOW, a WDT Reset occurs.

However, if your module has an EON EN25Q32C the GPIO9 pin will work. That Flash memory does not have a /HOLD function. The status register bits are quite different, I do not know if GPIO10 works.

Your success with this will vary with the SPI Flash memory used on your ESP module. There are a lot of differences between vendors.

More insight can be found in the library's Theory of Operation section of the readme.

See library SpiFlashUtils for "How to" and details on reclaiming the use of both GPIO9 and GPIO10.

In my writing these days I struggle to see the details (that are in my head) that did not make it to the page. If you happen to see an information gap (or confusing wording), please feel free to open an issue.

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